1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献_第6页

Design of experiments in BDD variable ordering: lessons learned BDD变量排序实验设计:经验教训

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289103

J. Harlow, F. Brglez

引用次数: 34

Verification of RTL generated from scheduled behavior in a high-level synthesis flow 验证高级合成流中由计划行为生成的RTL

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289080

P. Ashar, S. Bhattacharya, A. Raghunathan, A. Mukaiyama

{"title":"Verification of RTL generated from scheduled behavior in a high-level synthesis flow","authors":"P. Ashar, S. Bhattacharya, A. Raghunathan, A. Mukaiyama","doi":"10.1145/288548.289080","DOIUrl":"https://doi.org/10.1145/288548.289080","url":null,"abstract":"We propose a complete procedure for verifying register transfer logic against its scheduled behavior in a high level synthesis environment. Our proposal advances the state of the art because it is the first such verification procedure that is both complete and practical. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high level synthesis-performed manually or by means of high level synthesis software-proceeds from the algorithmic description of the design to structural RTL through a sequence of very well defined steps, each limited in its scope. The major contribution is the partitioning of the equivalence checking task into two simpler subtasks, verifying the validity of register sharing, and verifying correct synthesis of the RTL interconnect and control. While state space traversal is unavoidable for verifying validity of the register sharing, we automatically abstract out irrelevant portions of the design, significantly simplifying the task that must be performed by a back end model checker. The second task of verifying the RTL is not only shown to reduce to a combinational equivalence check, we present a novel and fast RTL technique for combinational equivalence check instead of using slower gate level techniques. The verification procedure has been applied to several large circuits, and is illustrated on the implementation of a sort algorithm.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116160829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

CMOS analog circuit stack generation with matching constraints 具有匹配约束的CMOS模拟电路堆栈生成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289056

R. Naiknaware, T. Fiez

引用次数: 4

Approximate Reachability Don't Cares for CTL model checking 近似可达性不关心CTL模型检查

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289053

In-Ho Moon, Jae-Young Jang, G. Hachtel, F. Somenzi, Jun Yuan, C. Pixley

{"title":"Approximate Reachability Don't Cares for CTL model checking","authors":"In-Ho Moon, Jae-Young Jang, G. Hachtel, F. Somenzi, Jun Yuan, C. Pixley","doi":"10.1145/288548.289053","DOIUrl":"https://doi.org/10.1145/288548.289053","url":null,"abstract":"RDCs (Reachability Don't Cares) can have a dramatic impact on the cost of CTL model checking (J. Yuan et al., 1997). Unfortunately, RDCs, being a global property, are often much more difficult to compute than the satisfying set of typical CTL formulas. We address this problem through the use of Approximate Reachability Don't Cares (ARDCs), computed with the algorithms developed for the VERITAS sequential synthesis package (H. ho et al., 1990; 1996). Approximate reachable states represent an upper bound on the set of true reachable states, and thus a lower bound on the set of unreachable (Don't Care) states. ARDCs can be 10X to 100X (or much more for very large circuits) cheaper to compute than RDCs, and in some cases have the same dramatic effect on CTL model checking as the real RDCs. We also discuss the application of ARDCs to the problem of exact computation of the RDCs themselves. Experiments on industrial benchmarks show that order of magnitude speedups are possible, and occur frequently. The experimental results presented strongly support our claim that ARDCs play a safe and important way out of a serious dilemma: RDCs are necessary for tractable model checking of many large circuits, but the computation of the RDCs themselves is often intractable. We include, and theoretically justify, significant extensions of the VERITAS algorithms, and show that they can be up to an order of magnitude faster, while computing a virtually identical upper bound.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121185897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

Accurate calculation of bit-level transition activity using word-level statistics and entropy function 使用字级统计和熵函数精确计算位级转移活动

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289095

E. Kyriakis-Bitzaros, S. Nikolaidis, A. Tatsaki

引用次数: 3

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits 时序电路的动态故障分解与诊断测试模式生成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288593

Colin E. Wood

引用次数: 11

Getting to the bottom of deep submicron 深入亚微米的底层

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288614

D. Sylvester, K. Keutzer

引用次数: 338

Estimating noise in RF systems 射频系统中的噪声估计

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288612

J. Roychowdhury, A. Demir

引用次数: 4

A simultaneous routing tree construction and fanout optimization algorithm 一种同时构建路由树和扇出优化算法

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289098

Amir H. Salek, J. Lou, Massoud Pedram

引用次数: 38

Node sampling: a robust RTL power modeling approach 节点采样:一种鲁棒的RTL功率建模方法

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289071

A. Bogliolo, L. Benini

引用次数: 18