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2018 IEEE 23rd European Test Symposium (ETS)最新文献

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Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests 在多周期测试中，用乐观的未指定的过渡故障覆盖未检测到的过渡故障点
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400704
I. Pomeranz
{"title":"Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests","authors":"I. Pomeranz","doi":"10.1109/ETS.2018.8400704","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400704","url":null,"abstract":"Transition faults require scan tests with two functional clock cycles between a scan-in and a scan-out operation to activate the faults and propagate their effects to observable outputs. Multicycle tests, with two or more functional clock cycles between scan operations, provide the following advantages. (1) They potentially increase the defect coverage by exercising the circuit at-speed for several functional clock cycles. (2) They allow test compaction to be achieved. (3) Multicycle tests can address features such as multiple clock domains and partial scan. (4) They create closer-to-functional operation conditions that are important for avoiding overtesting of delay faults.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131300234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects bist用于高密度三维互连缺陷的键后测试和电学分析
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400698
I. Jani, D. Lattard, P. Vivet, L. Arnaud, E. Beigné
{"title":"BISTs for post-bond test and electrical analysis of high density 3D interconnect defects","authors":"I. Jani, D. Lattard, P. Vivet, L. Arnaud, E. Beigné","doi":"10.1109/ETS.2018.8400698","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400698","url":null,"abstract":"Cu-Cu hybrid bonding offers very high density interconnects (pitch around 2 μm or less) in 3D stacking integrated circuits (HD 3D-IC), but the smaller the Cu pad size, the more the fabrication and bonding defects have an important impact on yield and performance. Defects such as bonding misalignment, micro-voids and contact defects at the copper surface, can affect the electrical characteristics and the life time of 3D-IC considerably. In this paper, we propose two complementary test and characterization structures dedicated to high density 3D-IC interconnects. The first test structure permits to measure the misalignment defect with a great accuracy and the second to measure the RC delay of a periodic signal applied to a daisy chain composed of 3D Cu-Cu interconnects. The measured misalignment values and propagation delays allows to detect Cu-Cu full open, misalignment, and micro-voids, in order to assess performance of high density 3D Integrated Circuit. Both test structures are implemented as BIST engines, which are integrated and controlled with IEEE 1687, for an overall negligible area cost.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121533370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Interconnect-aware tests to complement gate-exhaustive tests 互连感知测试以补充门穷举测试
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400699
I. Pomeranz, S. Venkataraman
{"title":"Interconnect-aware tests to complement gate-exhaustive tests","authors":"I. Pomeranz, S. Venkataraman","doi":"10.1109/ETS.2018.8400699","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400699","url":null,"abstract":"Gate-exhaustive and cell-aware tests are generated based on input patterns of cells in a design. While the tests provide thorough testing of the cells, the interconnects between them are tested only as input and output lines of cells. This paper defines cell-based faults that allow the interconnects to be tested more thoroughly within a uniform framework that only targets input patterns of cells. In contrast to a real cell that is part of the design, a dummy cell is used for defining interconnect-aware faults. Using a gate-level description of the circuit, a dummy cell contains an interconnect, an output gate of the real cell that drives it, and an input gate of the real cell that it drives. Experimental results for benchmark circuits show that many of the interconnect-aware faults are not detected accidentally by gate-exhaustive tests, and that the quality of the test set is improved by targeting interconnect-aware faults. Here, quality is measured by the numbers of detections of single stuck-at faults in a gate-level representation of the circuit.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132710558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ReiNN: Efficient error resilience in artificial neural networks using encoded consistency checks 使用编码一致性检查的人工神经网络的有效错误恢复
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400706
Sujay Pandey, Suvadeep Banerjee, A. Chatterjee
{"title":"ReiNN: Efficient error resilience in artificial neural networks using encoded consistency checks","authors":"Sujay Pandey, Suvadeep Banerjee, A. Chatterjee","doi":"10.1109/ETS.2018.8400706","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400706","url":null,"abstract":"In this research, a low cost error detection and correction approach is developed for multilayer perceptron networks, where checker neurons are used to encode hidden layer functions using independent training experiments. Error detection and correction is predicated on validating consistency properties of the encoded checks and shows that high coverage of injected errors can be achieved with extremely low computational overhead.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130591879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the mitigation of single event transients on flash-based FPGAs 基于flash的fpga中单事件瞬变的缓解
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400715
S. Azimi, B. Du, L. Sterpone
{"title":"On the mitigation of single event transients on flash-based FPGAs","authors":"S. Azimi, B. Du, L. Sterpone","doi":"10.1109/ETS.2018.8400715","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400715","url":null,"abstract":"Thanks to the immunity against Single Event Upsets in configuration memory, Flash-based FPGA is becoming widely adopted in mission- and safety-critical applications, such as in aerospace field. However, the decreasing of device feature size leads to an increasing of the device sensitivity regarding Single Event Transients (SETs). In this paper, we developed a new workflow to evaluate SET phenomena in a specific convergence case and introduce a new mitigation of SET pulse without introducing any performance penalization to the original netlist.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133717102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The impact of production defects on the soft-error tolerance of hardened latches 生产缺陷对硬化闩锁软误差容限的影响
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400694
S. Holst, Ruijun Ma, X. Wen
{"title":"The impact of production defects on the soft-error tolerance of hardened latches","authors":"S. Holst, Ruijun Ma, X. Wen","doi":"10.1109/ETS.2018.8400694","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400694","url":null,"abstract":"As modern technology nodes get more and more susceptible to soft-errors, various hardened latch cells have been proposed. The added redundancy used to tolerate transient faults in the field at the same time reduces the test coverage of cell-internal production defects. Moreover, the test escapes reduce the soft-error tolerance of the defective latches. This work introduces a new soft-error vulnerability metric called Post Test Vulnerability Factor that correctly measures the added vulnerability to transiant frults such as particle strikes caused by undiscovered production defects within hardened latches.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114461763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis 一种用于单细胞分析的高效容错阀微流控布线结构
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400712
Yasamin Moradi, K. Chakrabarty, Ulf Schlichtmann
{"title":"An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis","authors":"Yasamin Moradi, K. Chakrabarty, Ulf Schlichtmann","doi":"10.1109/ETS.2018.8400712","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400712","url":null,"abstract":"Single-cell analysis is used to gain insights into diseases such as cancer. Recently, a hybrid microfluidic platform was proposed for concurrent single-cell analysis on thousands of heterogeneous cells. In this design, barcoding droplets are routed using a valve-based routing fabric to label the input cells. The fault-tolerance of this routing fabric has also been studied and a design technique for implementing a fault-tolerant crossbar has been proposed. However, prior work leads to a significant increase in fabric size and a decrease in cell-analysis performance. We address the above drawbacks and introduce a low-overhead design technique for achieving fault-tolerance, while maintaining the efficiency of the cell-analysis platform. We show that the proposed method is optimal in that it minimizes the overhead in terms of fabric size. We also show that the new design outperforms the previous solution in terms of cell-analysis performance.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115596650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and testing methodologies for true random number generators towards industry certification 面向行业认证的真随机数生成器的设计和测试方法
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400697
J. Balasch, F. Bernard, V. Fischer, Miloš Grujić, Marek Laban, O. Petura, Vladimir Rožić, Gerard van Battum, I. Verbauwhede, M. Wakker, Bohan Yang
{"title":"Design and testing methodologies for true random number generators towards industry certification","authors":"J. Balasch, F. Bernard, V. Fischer, Miloš Grujić, Marek Laban, O. Petura, Vladimir Rožić, Gerard van Battum, I. Verbauwhede, M. Wakker, Bohan Yang","doi":"10.1109/ETS.2018.8400697","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400697","url":null,"abstract":"The objective of this paper is to provide insight on the design, evaluation and testing of modern True Random Number Generators (TRNGs) aimed towards certification. We discuss aspects related to each of these stages by means of two illustrative TRNG designs: PLL-TRNG and DC-TRNG. Topics covered in the paper include: the importance of formal security evaluations based on a stochastic model of the entropy source, the development of suitable and lightweight embedded tests to detect failures, the implementation and testing of TRNGs in dedicated FPGA platforms, and a robustness assessment to environmental and/or physical modifications.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131333630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262 故障检测强化方法使POST适用于超大型汽车MCU，符合ISO26262标准
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400707
Senling Wang, Y. Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
{"title":"Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262","authors":"Senling Wang, Y. Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima","doi":"10.1109/ETS.2018.8400707","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400707","url":null,"abstract":"To attain the requirement of ISO26262 standard, the POST for automotive MCU needs to achieve high Latent Fault (LF) metric (>90% for ASIL D) within limited test application time (TAT). In this paper, we propose a new DFT technique named Fault-Detection-Strengthened (FDS) method to enhance the effect of test pattern reduction of the multi-cycle test for shortening the TAT of POST, and develop an original in-house tool named FVP-TPI (Fault Vanishing Point-TPI) to implement the FDS method to automotive MCU. The evaluation results on a latest commercial automotive MCU (62M gates) confirm the effectiveness (test volume compaction) and the practicability (smaller hardware overhead, shorter period of DFT) of the method.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134018754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Extending post-silicon coverage measurement using time-multiplexed FPGA overlays 扩展后硅覆盖测量使用时间复用FPGA覆盖
2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400709
F. Eslami, Eddie Hung, S. Wilton
{"title":"Extending post-silicon coverage measurement using time-multiplexed FPGA overlays","authors":"F. Eslami, Eddie Hung, S. Wilton","doi":"10.1109/ETS.2018.8400709","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400709","url":null,"abstract":"Test coverage has emerged as an essential metric for evaluating the effectiveness of both pre-silicon verification and post-silicon validation. Evaluating coverage post-silicon is difficult due to the lack of visibility into the internal operation of integrated circuits. Adding coverage monitors to a design consumes a significant amount of chip area. Field-Programmable Gate Arrays (FPGAs) are commonly deployed as a rapid prototyping platform to accelerate the validation of digital designs, and though they share same visibility challenges as post-silicon, recent work have proposed the use of overlays to improve debug effectiveness. In this paper, we describe how this emerging debug technology can be re-purposed to also implement coverage monitors in a time-multiplexed fashion to evaluate coverage at post-silicon.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123833569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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