2018 IEEE 23rd European Test Symposium (ETS)最新文献_第3页

Methodology for determining the influencing factors of lifetime variation for power devices 电力装置寿命变化影响因素的确定方法

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400710

Ciprian V. Pop, Andi Buzo, G. Pelz, H. Cucu, C. Burileanu

{"title":"Methodology for determining the influencing factors of lifetime variation for power devices","authors":"Ciprian V. Pop, Andi Buzo, G. Pelz, H. Cucu, C. Burileanu","doi":"10.1109/ETS.2018.8400710","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400710","url":null,"abstract":"This paper proposes a method for explanation of the lifetime variation of power devices using data from different test stages. Understanding the lifetime variation is very useful in qualification, as well as in the characterization process, in order to improve the robustness of the power devices or to estimate more accurately the minimum guaranteed lifetime. Moreover, it helps design engineers better understand the root causes of the lifetime variation and use this knowledge to improve the performances of new power devices. In the proposed methodology, the variation of the lifetime is explained by the electrical parameters, measured before the stress-test. The Sensitivity Analysis presented here has the advantage of being simple and fast. It can be applied even when the number of test-runs is less than the number of factors. Moreover, it reveals not only linear correlations, but also quadratic effects and 2nd and 3rd order interactions. Eventually, the method provides the top of the most relevant electrical parameters which explain the lifetime variation. The validation of this approach has shown that 72% of the lifetime variation can be explained by the initial values of 5 electrical parameters.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127753224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Detection of IJTAG attacks using LDPC-based feature reduction and machine learning 基于ldpc的特征约简和机器学习的IJTAG攻击检测

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400684

Xuanle Ren, Shawn Blanton, V. Tavares

{"title":"Detection of IJTAG attacks using LDPC-based feature reduction and machine learning","authors":"Xuanle Ren, Shawn Blanton, V. Tavares","doi":"10.1109/ETS.2018.8400684","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400684","url":null,"abstract":"IEEE 1687 standard (IJTAG), as an extension to the IEEE 1149.1, facilitates efficient access to embedded instruments by supporting reconfigurable scan networks. Specifically, IJTAG allows each IP to be wrapped by a test data register (TDR) whose access is controlled by a segment insertion bit (SIB) or a scan-mux control bit (SCB). Because the TDRs and the SIB/SCB network are typically not public, but critical for accessing embedded instruments, they might be used for illegitimate purposes, such as dumping credential data and reverse engineering IP design. Machine learning has been proposed to detect such attacks, but the large number of instruments and parallel execution enabled by the IJTAG produce high-dimensional data, which poses a challenge to on-chip detection. In this paper, we propose to reduce the high-dimensional but sparse data using a low-density parity-check (LDPC) matrix. Experiments using a modified version of the OpenSPARC T2 to include IJTAG functionality demonstrate that the use of feature reduction eliminates 91% of the features, leading to 43% reduction in circuit size without affecting detection accuracy. Also, the on-chip detector adds moderate overhead (∼ 8%) to the IJTAG.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121788700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm 65纳米低压sram的感测放大器偏置特性和测试含义

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400696

Dhruv Rajendra Patel, Derek Wright, M. Sachdev

引用次数: 0

Challenges in Cell-Aware Test 细胞感知测试的挑战

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400700

S. P. Dixit, Divyeshkumar Dhanjibhai Vora, Ke Peng

{"title":"Challenges in Cell-Aware Test","authors":"S. P. Dixit, Divyeshkumar Dhanjibhai Vora, Ke Peng","doi":"10.1109/ETS.2018.8400700","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400700","url":null,"abstract":"Physical defects like opens and bridging defects can occur during the fabrication process of integrated circuits. The logic level abstraction of these physical defects, named fault models like stuck-at, transition, bridge, and small-delay defect, have been proposed, and are widely used in the industry for Automatic Test Pattern Generation (ATPG). However, as the technology moves to increasingly smaller geometries, these fault models and their associated test patterns are becoming less effective. The reason behind this is that existing fault models only consider faults on cell inputs and outputs, plus the interconnects between them. A growing number of defects occur within the cells, which are not explicitly targeted by traditional ATPG. N-detect algorithms can potentially test such defects by generating multiple patterns which detect cell-internal defects randomly. Cell-Aware Test (CAT) tries to solve this problem by uniquely targeting every possible internal defect. This is done via a series of analog simulations of all possible input combinations for all identified possible defects, which come at a significant runtime penalty. This paper shows a comparison of the static and transition patterns that are generated by the CAT methodology and the traditional ATPG for different library and cell parameters. This paper also aims to throw light on the quality concerns of the generated User Defined Fault Model (UDFM) by comparing results while varying different parameters of analog simulations, which reflect the variation due to Process, Voltage and Temperature (PVT). The increase in performance, pattern count and test coverage with respect to two Arm designs is also presented, which reflects the actual cost and gains of the CAT model over traditional ATPG.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Modeling and testing comparison faults of memristive ternary content addressable memories 忆性三元内容可寻址存储器的比较故障建模与测试

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400695

Li-Wei Deng, Jin-Fu Li, Yong-Xiao Chen

引用次数: 2

Towards the formal verification of security properties of a Network-on-Chip router 对片上网络路由器安全特性的形式化验证

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400692

Martha Johanna Sepúlveda, Damian Aboul-Hassan, G. Sigl, B. Becker, M. Sauer

引用次数: 19

On no-reference on-line error-tolerability testing for videos 视频无参考在线容错测试研究

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400711

Tong-Yu Hsieh, Shang-En Chan, Chi-Hsuan Ho

引用次数: 2

ADC test methods using an impure stimulus: A survey 使用非纯刺激的ADC测试方法:综述

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400687

J. Schat

引用次数: 5

A software reconfigurable assertion checking unit for run-time error detection 用于运行时错误检测的软件可重构断言检查单元

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400691

Yumin Zhou, S. Burg, O. Bringmann, W. Rosenstiel

引用次数: 2

Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits 毫米波电路非侵入式机器学习间接测试辅助测试设计

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI: 10.1109/ETS.2018.8400689

F. Cilici, M. Barragán, S. Mir, E. Lauga-Larroze, S. Bourdel

引用次数: 8