Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm

Abstract

Variability in offset voltage, bitcell transistor conductance, and leakage currents can lead to marginal and intermittent failures in low-voltage SRAMs. In this paper, we develop a model of these marginal faults that includes such sense amplifier and bitcell variability. Using simulations and measurement data from a 65 nm test chip, we investigate the likelihood of these failures and propose how to stimulate their occurrence during testing.