{"title":"Design of fault-tolerant neuromorphic computing systems","authors":"Mengyun Liu, Lixue Xia, Yu Wang, K. Chakrabarty","doi":"10.1109/ETS.2018.8400693","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400693","url":null,"abstract":"Neuromorphic computing is rapidly becoming mainstream, and Resistive Random Access Memory (RRAM) and RRAM-based computing systems (RCS) provide a promising hardware implementation of neuromorphic computing. This emerging computing system helps us to realize vector-matrix multiplications in a time complexity of 0(1), and it improves energy efficiency dramatically. However, due to the immature fabrication process, RCS is susceptible to defects; the resulting errors lead to a significant accuracy drop in neuromorphic computing applications. In order to take advantage of RCS in practical applications, fault-tolerant design is necessary. We present a survey of fault-tolerant designs for RRAM-based neuromorphic computing systems. We first describe RRAM-based crossbars and their role in neuromorphic computing systems. Following this, we classify fault models into different categories, and review the test solutions. Subsequently, the framework of fault-tolerant design for RCS is presented, which contains an online testing phase and a fault-tolerant training phase. The techniques proposed for these two phases are classified and explained to highlight their similarities and differences. The methods reviewed in this survey represent recent trends in fault-tolerant designs of RCS, and are expected motivate further research in this field.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114213956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware Trojan detection using path delay order encoding with process variation tolerance","authors":"Xiaotong Cui, Kaijie Wu, R. Karri","doi":"10.1109/ETS.2018.8400708","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400708","url":null,"abstract":"The outsourcing for fabrication introduces security threats, namely hardware Trojans (HTs). Many design-for-trust (DFT) techniques have been proposed to address such threats. However, many HT detection techniques are not effective due to the dependence on golden chips, limitation of useful information available and process variations. In this paper, we data-mine on path delay information and propose a variation-tolerant path delay order encoding technique to detect HTs.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126888344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Covering hard-to-detect defects by thermal quorum sensing","authors":"Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen","doi":"10.1109/ETS.2018.8400705","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400705","url":null,"abstract":"With the advent of highly complex and dense modern CMOS circuits, defects caused by parametric and process variations, e.g., are more and more difficult to detect. Many hard-to-detect defects not sensitized through the critical paths can easily escape from the conventional testing methods. In order to reduce the product defect level, we introduce the notion of quorum sensing (QS) to circuit testing (sensing) for improving the quality and reliability. The proposed thermal quorum sensing (TQS) mechanism triggers a thermal chain reaction to expose the subtle variations in the circuit due to small defects, which can be observed by the common cell population behavior. A model is introduced to charactize the feature of TQS on circuit. The simualtion result verified by the ISCAS s9234 benchmark with 45nm CMOS standard cell library shows when the number of small defects injected is more than 489, the difference in total current will be higher than 2.08mA. It can discover the subtle faults compared with other state-of-the-art or traditional testing methods.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126470566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sukanta Bhattacharjee, Jack Tang, Mohamed Ibrahim, K. Chakrabarty, R. Karri
{"title":"Locking of biochemical assays for digital microfluidic biochips","authors":"Sukanta Bhattacharjee, Jack Tang, Mohamed Ibrahim, K. Chakrabarty, R. Karri","doi":"10.1109/ETS.2018.8400686","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400686","url":null,"abstract":"It is expected that as digital microfluidic biochips (DMFBs) mature, the hardware design flow will begin to resemble the current practice in the semiconductor industry: design teams send chip layouts to third party foundries for fabrication. These foundries are untrusted, and threaten to steal valuable intellectual property (IP). In a DMFB, the IP consists of not only hardware layouts, but also of the biochemical assays (bioassays) that are intended to be executed on-chip. DMFB designers therefore must defend these protocols against theft. We propose to “lock” biochemical assays through random insertion of dummy mix-split operations, subject to several design rules. We experimentally evaluate the proposed locking mechanism, and show how a high level of protection can be achieved even on bioassays with low complexity. We offer guidance on the number of dummy mixsplits required to secure a bioassay for the lifetime of a patent.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115999845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daniele Rossi, V. Tenentes, S. Khursheed, S. Reddy
{"title":"Recycled IC detection through aging sensor","authors":"Daniele Rossi, V. Tenentes, S. Khursheed, S. Reddy","doi":"10.1109/ETS.2018.8400713","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400713","url":null,"abstract":"In this paper, we propose a novel technique to detect recycled ICs via an on-chip, coarse-grained aging sensor, which can be applied to low-power circuits featuring power gating. The sensor detects the increase in the power-rail discharge time of power-gated circuits, when the circuit enters the sleep condition. Through HSPICE simulations, we prove that power network discharge time (τdV) is extremely sensitive to the age of the circuit. Indeed, after only 1 month of operation, τdV increases by more than 3X and, after 1 year, its increase exceeds 7X. Our technique enables the detection of recycled ICs with a very high confidence and is a considerably more sensitive indicator of an aged device that alternative solutions relying on fine-grained performance degradation sensors.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"473 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114963978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu LI, Ming Shao, Hailong Jiao, A. Cron, S. Bhatia, E. Marinissen
{"title":"IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers","authors":"Yu LI, Ming Shao, Hailong Jiao, A. Cron, S. Bhatia, E. Marinissen","doi":"10.1109/ETS.2018.8400690","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400690","url":null,"abstract":"IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DfT standard to include a flexible parallel port (FPP): an optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121138583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic generation of in-circuit tests for board assembly defects","authors":"Harm van Schaaijk, M. Spierings, E. Marinissen","doi":"10.1109/ETS.2018.8400714","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400714","url":null,"abstract":"The components and the solder joints that are made during assembly to hold components to their printed circuit board can suffer from defects and therefore need to be tested. Many research papers on board-assembly testing focus on boundary scan test, processor-controlled test, or other powered digital testing techniques that mostly ignore the indispensable passive circuits and that can incur damage that could have been avoided by executing a non-powered test first. In-circuit testing is a non-powered test method that applies stimuli and measures responses using probe needles. However, often used self-learning solutions for designing these tests need a known-good-board, entailing significant disadvantages. In this paper, a software tool is described that automatically generates in-circuit tests based on the product design files, without requiring probe access on every net. Furthermore, the tool indicates where on the board fault coverage is not maximal, and hence where extra probe access will improve the test quality.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126428758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Machine learning applications in IC testing","authors":"H. Stratigopoulos","doi":"10.1109/ETS.2018.8400701","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400701","url":null,"abstract":"In recent years, a large number of works have surfaced demonstrating applications of machine learning in the field of integrated circuit testing. Many of these works showcase the effectiveness of machine learning compared to the current industry practice on actual case studies with industrial data. The aim of the paper is to offer a concise and comprehensive tutorial on machine learning applications in integrated circuit testing and to provide some practical recommendations for practitioners.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114203888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Atteya, M. Kochte, M. Sauer, Pascal Raiola, B. Becker, H. Wunderlich
{"title":"Online prevention of security violations in reconfigurable scan networks","authors":"A. Atteya, M. Kochte, M. Sauer, Pascal Raiola, B. Becker, H. Wunderlich","doi":"10.1109/ETS.2018.8400685","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400685","url":null,"abstract":"Modern systems-on-chip (SoC) designs are requiring more and more infrastructure for validation, debug, volume test as well as in-field maintenance and repair. Reconfigurable scan networks (RSNs), as allowed by IEEE 1687 (IJTAG) standard, provide flexible access to the infrastructure with low access latency. However, they can also pose a security threat to the system, by leaking information about the system state. In this paper, we present a protection method that monitors access and checks for violations of security properties online. The method prevents unauthorized access to sensitive and secure instruments. In addition, the system integrator can specify more complex security requirements, including giving multiple users different access privileges. Simultaneous accesses to multiple instruments, that would expose sensitive data to an untrusted core (e.g. from 3rd party vendors) or instrument, can be prohibited. The method does not require any change to the RSN architecture and is easily integrable with IP core designs. The area overhead with respect to the size of the RSN is below 6% and scales well with larger networks.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121560584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daniel Kraak, M. Taouil, S. Hamdioui, P. Weckx, F. Catthoor, A. Chatterjee, A. Singh, H. Wunderlich, Naghmeh Karimi
{"title":"Device aging: A reliability and security concern","authors":"Daniel Kraak, M. Taouil, S. Hamdioui, P. Weckx, F. Catthoor, A. Chatterjee, A. Singh, H. Wunderlich, Naghmeh Karimi","doi":"10.1109/ETS.2018.8400702","DOIUrl":"https://doi.org/10.1109/ETS.2018.8400702","url":null,"abstract":"Device aging is an important concern in nanoscale designs. Due to aging the electrical behavior of transistors embedded in an integrated circuit deviates from original intended one. This leads to performance degradation in the underlying device, and the ultimate device failure. This effect is exacerbated in emerging technologies. To be able to tailor effective aging mitigation schemes and improve the reliability of devices realized in cutting edge technologies, there is a need to accurately study the effect of aging in high performance industrial applications. According, this paper targets a high performance SRAM memory realized in 14nm FinFET technology and depicts how aging degrades the individual components of this memory as well as the interaction between them. Aging mitigation is critical not only from device reliability point of view but also regarding device security perspectives. It is essential to assure the security of the sensitive tasks performed by the security-sensitive circuits and to guarantee the security of information stored within these devices in the presence of aging. Accordingly in this paper, we also focus on aging-related security concerns and present the cases in which aging need to considered to preserve security.","PeriodicalId":223459,"journal":{"name":"2018 IEEE 23rd European Test Symposium (ETS)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116323587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}