IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Yu LI, Ming Shao, Hailong Jiao, A. Cron, S. Bhatia, E. Marinissen
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引用次数: 6

Abstract

IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DfT standard to include a flexible parallel port (FPP): an optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist.
IEEE标准P1838的灵活并行端口及其规范与谷歌的协议缓冲区
IEEE Std P1838是用于3D多模具堆叠组件的3D测试进入模具的DfT标准,正在开发中。P1838是第一个包含灵活并行端口(FPP)的DfT标准:可选的,可扩展的多位(“并行”)测试访问机制,与强制性的一位(“串行”)端口相比,提供更高的测试访问带宽。在本文中,我们描述了P1838的FPP,并提出了一种基于Google协议缓冲区(PBs)的正式FPP规范语言,该语言有可能成为标准的一部分。对于一个实际的FPP示例,我们提供了它的正式规范。最后,我们报告了一个演示软件工具,该工具使用pbs生成的数据访问例程开发,可将FPP规范转换为相应的Verilog网表。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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