65纳米低压sram的感测放大器偏置特性和测试含义

2018 IEEE 23rd European Test Symposium (ETS) Pub Date : 2018-05-01 DOI:10.1109/ETS.2018.8400696

Dhruv Rajendra Patel, Derek Wright, M. Sachdev

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引用次数: 0

摘要

偏置电压、位单元晶体管电导和漏电流的可变性可能导致低压sram的边际和间歇性故障。在本文中，我们建立了一个包含这种感测放大器和位元变异性的边缘故障模型。利用模拟和来自65nm测试芯片的测量数据，我们研究了这些故障的可能性，并提出了如何在测试过程中刺激它们的发生。

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Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm

Variability in offset voltage, bitcell transistor conductance, and leakage currents can lead to marginal and intermittent failures in low-voltage SRAMs. In this paper, we develop a model of these marginal faults that includes such sense amplifier and bitcell variability. Using simulations and measurement data from a 65 nm test chip, we investigate the likelihood of these failures and propose how to stimulate their occurrence during testing.

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2018 IEEE 23rd European Test Symposium (ETS)

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