Extending post-silicon coverage measurement using time-multiplexed FPGA overlays

Abstract

Test coverage has emerged as an essential metric for evaluating the effectiveness of both pre-silicon verification and post-silicon validation. Evaluating coverage post-silicon is difficult due to the lack of visibility into the internal operation of integrated circuits. Adding coverage monitors to a design consumes a significant amount of chip area. Field-Programmable Gate Arrays (FPGAs) are commonly deployed as a rapid prototyping platform to accelerate the validation of digital designs, and though they share same visibility challenges as post-silicon, recent work have proposed the use of overlays to improve debug effectiveness. In this paper, we describe how this emerging debug technology can be re-purposed to also implement coverage monitors in a time-multiplexed fashion to evaluate coverage at post-silicon.