2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)最新文献

Verifying Bio-Electronic Systems 验证生物电子系统

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139574

Joseline Heuer, Rene Krenz-Baath, R. Obermaisser

引用次数: 0

Open Automation Framework for Complex Parametric Electrical Simulations 复杂参数电气仿真的开放式自动化框架

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139409

Sergio Vinagrero Gutierrez, Pietro Inglese, G. D. Natale, E. Vatajelu

引用次数: 1

Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits 支持近似电路的CNN加速器推理能量预测

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139724

Michal Pinos, Vojtěch Mrázek, L. Sekanina

{"title":"Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits","authors":"Michal Pinos, Vojtěch Mrázek, L. Sekanina","doi":"10.1109/DDECS57882.2023.10139724","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139724","url":null,"abstract":"Design methodologies developed for optimizing hardware implementations of convolutional neural networks (CNN) or searching for new hardware-aware neural architectures rely on the fast and reliable estimation of key hardware parameters, such as the energy needed for one inference. Utilizing approximate circuits in hardware accelerators of CNNs faces the designers with new problems during their simulation — commonly used tools (TimeLoop, Accelergy, Maestro) do not support approximate arithmetic operations. This work addresses the fast and efficient prediction of consumed energy in hardware accelerators of CNNs that utilize approximate circuits such as approximate multipliers. First, we extend the state-of-the-art software frameworks TimeLoop and Accelergy to predict the inference energy when exact multipliers are replaced with various approximate implementations. The energies obtained using the modified tools are then considered the ground truth (reference) values. Then, we propose and evaluate, using two accelerators (Eyeriss and Simba) and two types of networks (CNNs generated by EvoApproxNAS and standard ResNet CNNs), two predictors of inference energy. We conclude that a simple predictor based on summing the energies needed for all multiplications highly correlates with the reference values if the CNN’s architecture is fixed. For complex CNNs with variable architectures typically generated by neural architecture search algorithms, a more sophisticated predictor based on a machine learning model has to be employed. The proposed predictors are 420-533× faster than reference solutions.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133892049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bits, Flips and RISCs 位，翻转和risc

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139331

Nicolas Gerlin, Endri Kaja, F. Vargas, Li Lu, A. Breitenreiter, Junchao Chen, Markus Ulbricht, Maribel Gomez, Ares Tahiraga, S. Prebeck, E. Jentzsch, M. Krstic, W. Ecker

{"title":"Bits, Flips and RISCs","authors":"Nicolas Gerlin, Endri Kaja, F. Vargas, Li Lu, A. Breitenreiter, Junchao Chen, Markus Ulbricht, Maribel Gomez, Ares Tahiraga, S. Prebeck, E. Jentzsch, M. Krstic, W. Ecker","doi":"10.1109/DDECS57882.2023.10139331","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139331","url":null,"abstract":"Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In safety-critical applications, the risks of such events should be managed to prevent injuries or material damage. This paper provides a comprehensive overview of the challenges associated with designing and verifying safe and reliable systems, as well as the potential of the RISC-V architecture in addressing these challenges.We present several state-of-the-art safety and reliability verification techniques in the design phase. These include a highly-automated verification flow, an automated fault injection and analysis tool, and an AI-based fault verification flow. Furthermore, we discuss core hardening and fault mitigation strategies at the design level. We focus on automated SoC hardening using model-driven development and resilient processing based on sensing and prediction for space and avionic applications.By combining these techniques with the inherent flexibility of the RISC-V architecture, designers can develop tailored solutions that balance cost, performance, and fault tolerance to meet the requirements of various safety-critical applications in different safety domains, such as avionics, automotive, and space. The insights and methodologies presented in this paper contribute to the ongoing efforts to improve the dependability of computing systems in safety-critical environments.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128386102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures 用于内存处理架构的灵活神经加速器

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139567

Ali Monavari Bidgoli, Sepideh Fattahi, Seyyed Hossein Seyyedaghaei Rezaei, M. Modarressi, M. Daneshtalab

{"title":"NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures","authors":"Ali Monavari Bidgoli, Sepideh Fattahi, Seyyed Hossein Seyyedaghaei Rezaei, M. Modarressi, M. Daneshtalab","doi":"10.1109/DDECS57882.2023.10139567","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139567","url":null,"abstract":"The performance of microprocessors under many modern workloads is mainly limited by the off-chip memory bandwidth. The emerging process-in-memory paradigm present a unique opportunity to reduce data movement overheads by moving computation closer to memory. State-of-the-art processing-in-memory proposals stack a logic layer on top of one or multiple memory layers in a 3D fashion and leverage the logic layer to build near-memory processing units. Such processing units are either application-specific accelerators or general-purpose cores. In this paper, we present NeuroPIM, a new processing-in-memory architecture that uses a neural network as the memory-side general-purpose accelerator. This design is mainly motivated by the observation that in many real-world applications, some program regions, or even the entire program, can be replaced by a neural network that is learned to approximate the program’s output. NeuroPIM benefits from both the flexibility of general-purpose processors and superior performance of application-specific accelerators. Experimental results show that NeuroPIM provides up to 41% speedup over a processor-side neural network accelerator and up to 8x speedup over a general-purpose processor.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125365158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator 深度神经网络加速器的弹性-性能权衡分析

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139704

Salvatore Pappalardo, A. Ruospo, Ian O’Connor, B. Deveautour, Ernesto Sánchez, A. Bosio

引用次数: 0

Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes 减少中间节点数的高效二值决策图处理

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139373

Rune Krauss, Mehran Goli, R. Drechsler

引用次数: 0

MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers 左旋多巴诱导运动障碍分类器节能硬件加速器的多目标设计

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139399

Martin Hurta, Vojtěch Mrázek, Michaela Drahosova, L. Sekanina

{"title":"MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers","authors":"Martin Hurta, Vojtěch Mrázek, Michaela Drahosova, L. Sekanina","doi":"10.1109/DDECS57882.2023.10139399","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139399","url":null,"abstract":"Taking levodopa, a drug used to treat symptoms of Parkinson’s disease, is often connected with severe side effects, known as Levodopa-induced dyskinesia (LID). It can fluctuate in severity throughout the day and thus is difficult to classify during a short period of a physician’s visit. A low-power wearable classifier enabling long-term and continuous LID classification would thus significantly help with LID detection and dosage adjustment. This paper deals with an automated design of energy-efficient hardware accelerators of LID classifiers that can be implemented in wearable devices. The accelerator consists of a feature extractor and a classification circuit co-designed using genetic programming (GP). We also introduce and evaluate a fast and accurate energy consumption estimation method for the target architecture of considered classifiers. In a multiobjective design scenario, GP evolves solutions showing the best trade-offs between accuracy and energy. Compared to the state-of-the-art solutions, the proposed method leads to classifiers showing a comparable accuracy while the energy consumption is reduced by 49 %.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132836873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Supporting analog design for reliability by efficient provision of reliability information to designers 通过向设计人员提供有效的可靠性信息，支持模拟设计的可靠性

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139428

F. A. Velarde Gonzalez, L. Hahne, Katrin Ortstein, André Lange, Sonja Crocoll

引用次数: 0

Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug Candidates 独立区域优化ASIC标签供电和可编程的光识别新的候选药物

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139720

Dominic Korner, Andreas Kramer, K. Hofmann, F. Hausch

引用次数: 0