NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures

Ali Monavari Bidgoli, Sepideh Fattahi, Seyyed Hossein Seyyedaghaei Rezaei, M. Modarressi, M. Daneshtalab
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Abstract

The performance of microprocessors under many modern workloads is mainly limited by the off-chip memory bandwidth. The emerging process-in-memory paradigm present a unique opportunity to reduce data movement overheads by moving computation closer to memory. State-of-the-art processing-in-memory proposals stack a logic layer on top of one or multiple memory layers in a 3D fashion and leverage the logic layer to build near-memory processing units. Such processing units are either application-specific accelerators or general-purpose cores. In this paper, we present NeuroPIM, a new processing-in-memory architecture that uses a neural network as the memory-side general-purpose accelerator. This design is mainly motivated by the observation that in many real-world applications, some program regions, or even the entire program, can be replaced by a neural network that is learned to approximate the program’s output. NeuroPIM benefits from both the flexibility of general-purpose processors and superior performance of application-specific accelerators. Experimental results show that NeuroPIM provides up to 41% speedup over a processor-side neural network accelerator and up to 8x speedup over a general-purpose processor.
用于内存处理架构的灵活神经加速器
在许多现代工作负载下,微处理器的性能主要受到片外存储器带宽的限制。正在出现的内存中的进程范式提供了一个独特的机会,通过将计算移到更靠近内存的位置来减少数据移动开销。最先进的内存处理建议以3D方式将逻辑层堆叠在一个或多个内存层之上,并利用逻辑层构建近内存处理单元。这些处理单元要么是特定于应用程序的加速器,要么是通用核心。在本文中,我们提出了一种新的内存处理架构NeuroPIM,它使用神经网络作为内存端通用加速器。这种设计的主要动机是观察到,在许多现实世界的应用中,一些程序区域,甚至整个程序,可以被学习来近似程序输出的神经网络所取代。NeuroPIM受益于通用处理器的灵活性和特定应用程序加速器的卓越性能。实验结果表明,与处理器端神经网络加速器相比,NeuroPIM提供了高达41%的加速,比通用处理器提供了高达8倍的加速。
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