2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)最新文献_第2页

DDECS 2023 Cover Page DDECS 2023封面

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/ddecs57882.2023.10139416

引用次数: 0

Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype Xtensa虚拟样机硬件性能指标评估

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10138942

A. Omotosho, Sirine IIahi, Ernesto Cristopher Villegas Castillo, Christian Hammer, C. Sauer

引用次数: 0

APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors 估价师:采用近似误差的DNN故障恢复分析

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139468

Mahdi Taheri, Mohammad Hasan Ahmadilivani, M. Jenihhin, M. Daneshtalab, J. Raik

{"title":"APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors","authors":"Mahdi Taheri, Mohammad Hasan Ahmadilivani, M. Jenihhin, M. Daneshtalab, J. Raik","doi":"10.1109/DDECS57882.2023.10139468","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139468","url":null,"abstract":"Nowadays, the extensive exploitation of Deep Neural Networks (DNNs) in safety-critical applications raises new reliability concerns. In practice, methods for fault injection by emulation in hardware are efficient and widely used to study the resilience of DNN architectures for mitigating reliability issues already at the early design stages. However, the state-of-the-art methods for fault injection by emulation incur a spectrum of time-, design-and control-complexity problems. To overcome these issues, a novel resiliency assessment method called APPRAISER is proposed that applies functional approximation for a non-conventional purpose and employs approximate computing errors for its interest. By adopting this concept in the resiliency assessment domain, APPRAISER provides thousands of times speed-up in the assessment process, while keeping high accuracy of the analysis. In this paper, APPRAISER is validated by comparing it with state-of-the-art approaches for fault injection by emulation in FPGA. By this, the feasibility of the idea is demonstrated, and a new perspective in resiliency evaluation for DNNs is opened.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133837403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations 基于电阻的抗pvt鲁棒PUF结构设计与评估

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139352

Carl Riehm, Christoph Frisch, Florin Burcea, Matthias Hiller, Michael Pehl, R. Brederlow

引用次数: 1

Optimizing Packet Classification on FPGA 基于FPGA的分组分类优化

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139668

Michal Kekely, J. Korenek

{"title":"Optimizing Packet Classification on FPGA","authors":"Michal Kekely, J. Korenek","doi":"10.1109/DDECS57882.2023.10139668","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139668","url":null,"abstract":"Packet classification is a crucial time-critical operation for many different networking tasks ranging from switching or routing to monitoring and security devices like firewalls or IDS. Accelerated architectures implementing packet classification must satisfy the ever-growing demand for current high-speed networks. However, packet classification is generally used together with other packet processing algorithms, which decreases the available hardware resources on the FPGA chip. The introduction of the P4 language requires the packet classification to be even more flexible while maintaining a high throughput with limited resources. Thus, we need flexible and high-performance architectures to balance processing speed and hardware resources for specific types of rules. DCFL algorithm provides high performance and flexibility. Therefore, we propose optimizations to the DCFL algorithm and overall packet processing hardware architecture. The goal is to maximize the throughput and minimize the resource strain. The main idea of the approach is to analyze the ruleset, identify some conflicting rules and offload these rules to other hardware modules. This approach allows us to process packets faster, even in the worst-case scenarios. Moreover, we can fit more packet processing into the FPGA and fine-tune the packet processing architecture to meet a specific network application’s throughput and resource demands. With the proposed optimizations we can achieve up to a 76 % increase in the throughput of the packet classification. Alternatively, we can achieve up to a 37 % decrease in resources needed.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123917745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DDECS 2023 Organizing Committee DDECS 2023组委会

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/ddecs57882.2023.10139699

引用次数: 0

A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators 基于残差的低成本RNN加速器容错方案

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139388

Nooshin Nosrati, Z. Navabi

{"title":"A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators","authors":"Nooshin Nosrati, Z. Navabi","doi":"10.1109/DDECS57882.2023.10139388","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139388","url":null,"abstract":"Acceleration and power reduction requirements are usually the main constraints for the design of Artificial Neural Network (ANN) accelerators. However, in the case of safety-critical applications like autonomous driving, reliability takes precedence over other requirements. Although ANN algorithms provide a degree of inherent resiliency, the hardware part is still vulnerable to faults and may cause catastrophic failures. This paper proposes using residue codes for detecting soft errors in Recurrent Neural Networks (RNNs), and in particular, Long Short-Term Memory (LSTM) networks. We attach Concurrent Error Detection (CED) hardware units to an entire LSTM structure or its substructures. Depending on the granularity of the components to which they are applied, CEDs are referred to as coarse-grain or fine-grain CEDs. The simulation results show that in fault detection rate and misprediction coverage rate, fine-grain CEDs have a better performance than coarse-grain. Specifically, fine-grain residue-based CEDs provide up to 97% fault detection for extremely large (10-2) bit error rates. Moreover, they reduce the misprediction rate by 84% compared to unprotected LSTM.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125439431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LUTIC: A CRAM-based Architecture for Power Failure Resilient In-Memory Computing LUTIC:一种基于ram的电源故障弹性内存计算架构

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139576

K. Akhunov, K. Yıldırım

引用次数: 0

A Comprehensive Analysis of Transient Errors on Systolic Arrays 收缩阵列瞬态误差的综合分析

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139763

Eleonora Vacca, S. Azimi, L. Sterpone

引用次数: 0

A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel 凿子中可配置混合精度卷积处理单元生成器

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139758

Jure Vreča, Anton Biasizzo

引用次数: 0