2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)最新文献_第4页

Characterization of Interconnect Fault Effects in SRAM-based FPGAs 基于sram的fpga互连故障效应的表征

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139343

Christian Fibich, M. Horauer, R. Obermaisser

{"title":"Characterization of Interconnect Fault Effects in SRAM-based FPGAs","authors":"Christian Fibich, M. Horauer, R. Obermaisser","doi":"10.1109/DDECS57882.2023.10139343","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139343","url":null,"abstract":"The configurable interconnect of SRAM-based FPGAs makes up a significant portion of their configuration, and thus exposes a large attack surface to single-event upsets. A better understanding of the behavior of FPGA interconnects under the presence of these faults may allow fault injection campaigns and reliability estimation techniques to treat some interconnect faults as more serious than others. This work proposes an approach to (1) analyze the interconnect configuration of a given FPGA technology to deduce the logical effects caused by single-bit flips and (2) to characterize the effects of such faults on routes implemented on a given FPGA technology. These approaches are illustrated in case studies on two FPGA technologies: Xilinx 7 Series and Lattice iCE40. Characterization of interconnect faults on these devices revealed that certain subcategories of interconnect fault types are far more critical than others, allowing more focused fault injection campaigns. Applying this knowledge to three benchmark designs implemented on a Xilinx 7 Series device shows that fault injection effort can be significantly reduced by skipping bits that are unlikely to critically impact the design.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121481313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques 基于伪布尔优化技术的逻辑锁定机制质量评估

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139590

M. Merten, Muhammad Hassan, R. Drechsler

{"title":"Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques","authors":"M. Merten, Muhammad Hassan, R. Drechsler","doi":"10.1109/DDECS57882.2023.10139590","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139590","url":null,"abstract":"Nowadays, the manufacturing of Integrated Circuits (ICs) is highly distributed over different foundries yielding untrustworthy supply chains. This circumstance leads to concerns regarding the security, privacy, and reliability of the fabricated ICs, e.g., malicious usage and counterfeiting. Logic Locking (LL) is a prominent protection technique to safeguard against such concerns. Recently, the emerging technology of Reconfigurable Field-Effect Transistors (RFETs) has been utilized to implement new mechanisms based on Polymorphic Logic Gates (PLGs) to protect Intellectual Property (IP). The mechanisms’ assessment is indispensable to reinforce the newly introduced logic obfuscation and, hence, avoid any security breaches. So far, formal SAT-based and approximate Hamming Distance (HD)-based assessment techniques have been used for determining the protection quality. While the approximate and formal approaches can detect many security threats [1], they are still unable to detect optimization-based attacks. This work proposes a novel formal approach based on Pseudo Boolean Optimization (PBO) to assess the quality of LL structures for sequential circuits, enabling the detection of currently unconsidered security breaches. In particular, the proposed approach leverages formal techniques to analyze the key and state space of a sequential circuit to evaluate the security against optimization-based attacks. The experimental evaluation validates that the proposed scheme unveils weaknesses of the protection structure, which remain undetected when using existing techniques.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128843400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Split-Et-Impera: A Framework for the Design of Distributed Deep Learning Applications Split-Et-Impera:分布式深度学习应用程序设计框架

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-03-22 DOI: 10.1109/DDECS57882.2023.10139711

Luigi Capogrosso, Federico Cunico, M. Lora, M. Cristani, F. Fummi, D. Quaglia

{"title":"Split-Et-Impera: A Framework for the Design of Distributed Deep Learning Applications","authors":"Luigi Capogrosso, Federico Cunico, M. Lora, M. Cristani, F. Fummi, D. Quaglia","doi":"10.1109/DDECS57882.2023.10139711","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139711","url":null,"abstract":"Many recent pattern recognition applications rely on complex distributed architectures in which sensing and computational nodes interact together through a communication network. Deep neural networks (DNNs) play an important role in this scenario, furnishing powerful decision mechanisms, at the price of a high computational effort. Consequently, powerful state-of-the-art DNNs are frequently split over various computational nodes, e.g., a first part stays on an embedded device and the rest on a server. Deciding where to split a DNN is a challenge in itself, making the design of deep learning applications even more complicated. Therefore, we propose Split-Et-Impera, a novel and practical framework that i) determines the set of the best-split points of a neural network based on deep network interpretability principles without performing a tedious try-and-test approach, ii) performs a communication-aware simulation for the rapid evaluation of different neural network rearrangements, and iii) suggests the best match between the quality of service requirements of the application and the performance in terms of accuracy and latency time.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128462411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package HermesBDD:一个多核多平台二元决策图包

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-03-22 DOI: 10.1109/DDECS57882.2023.10139480

Luigi Capogrosso, Luca Geretti, M. Cristani, F. Fummi, T. Villa

{"title":"HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package","authors":"Luigi Capogrosso, Luca Geretti, M. Cristani, F. Fummi, T. Villa","doi":"10.1109/DDECS57882.2023.10139480","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139480","url":null,"abstract":"BDDs are representations of a Boolean expression in the form of a directed acyclic graph. BDDs are widely used in several fields, particularly in model checking and hardware verification. There are several implementations for BDD manipulation, where each package differs depending on the application. This paper presents HermesBDD: a novel multi-core and multi-platform binary decision diagram package focused on high performance and usability. HermesBDD supports a static and dynamic memory management mechanism, the possibility to exploit lock-free hash tables, and a simple parallel implementation of the IF-THEN-ELSE procedure based on a higher-level wrapper for threads and futures. HermesBDD is completely written in C++ with no need to rely on external libraries and is developed according to software engineering principles for reliability and easy maintenance over time. We provide experimental results on the n-Queens problem, the de-facto SAT solver benchmark for BDDs, demonstrating a significant speedup of 18.73× over our non-parallel baselines, and a remarkable performance boost w.r.t. other state-of-the-art BDDs packages.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127266027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Counterfeit Chip Detection using Scattering Parameter Analysis 基于散射参数分析的伪造芯片检测

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-02-21 DOI: 10.1109/DDECS57882.2023.10139623

Maryam Saadat-Safa, Tahoura Mosavirik, Shahin Tajik

{"title":"Counterfeit Chip Detection using Scattering Parameter Analysis","authors":"Maryam Saadat-Safa, Tahoura Mosavirik, Shahin Tajik","doi":"10.1109/DDECS57882.2023.10139623","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139623","url":null,"abstract":"The increase in the number of counterfeit and recycled microelectronic chips in recent years has created significant security and safety concerns in various applications. Hence, detecting such counterfeit chips in electronic systems is critical before deployment in the field. Unfortunately, the conventional verification tools using physical inspection and side-channel methods are costly, unscalable, error-prone, and often incompatible with legacy systems. This paper introduces a generic non-invasive and low-cost counterfeit chip detection based on characterizing the impedance of the system’s power delivery network (PDN). Our method relies on the fact that the impedance of the counterfeit and recycled chips differs from the genuine ones. To sense such impedance variations confidently, we deploy scattering parameters, frequently used for impedance characterization of RF/microwave circuits. Our proposed approach can directly be applied to soldered chips on the system’s PCB and does not require any modifications on the legacy systems. To validate our claims, we perform extensive measurements on genuine and aged samples from two families of STMicroelectronics chips to assess the effectiveness of the proposed approach.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132737337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Digital Delay Model Supporting Large Adversarial Delay Variations 支持大对抗延迟变化的数字延迟模型

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-01-10 DOI: 10.1109/DDECS57882.2023.10139680

Daniel Öhlinger, U. Schmid

引用次数: 2