2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)最新文献_第3页

Hardware Acceleration of FHEW FHEW的硬件加速

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139347

Jonas Bertels, Michiel Van Beirendonck, Furkan Turan, I. Verbauwhede

引用次数: 3

Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models 基于学习决策树模型的黑箱系统数据驱动测试生成

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139633

Swantje Plambeck, Goerschwin Fey

引用次数: 0

Reducing Output Response Aliasing Using Boolean Optimization Techniques 使用布尔优化技术减少输出响应混叠

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139408

Robert Hülle, P. Fiser, Jan Schmidt

引用次数: 0

Active Wire Fences for Multitenant FPGAs 多租户fpga的有源线栅

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10138941

Ognjen Glamočanin, Anđela Koštić, Staša Kostić, Mirjana Stojilović

{"title":"Active Wire Fences for Multitenant FPGAs","authors":"Ognjen Glamočanin, Anđela Koštić, Staša Kostić, Mirjana Stojilović","doi":"10.1109/DDECS57882.2023.10138941","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10138941","url":null,"abstract":"When spatially shared among multiple tenants, field-programmable gate arrays (FPGAs) are vulnerable to remote power side-channel analysis attacks. Using carefully crafted on-chip voltage sensors, adversaries can extract secrets (e.g., encryption keys or the architectural parameters of neural network accelerators) from collocated tenants. A common countermeasure against power side-channel attacks is hiding; in hiding, the goal is to introduce noise and worsen the signal-to-noise ratio visible to the attacker. In a multitenant FPGA setting, hiding countermeasures can be implemented with an active fence placed between tenants. Previous work demonstrated the effectiveness of active fences built using NAND-based ROs. We enhance the state-of-the-art active fence implementation with novel wire-based power wasters, at no increase in resource overhead. Compared to an RO-based fence, our active wire fence makes the side-channel attack considerably more difficult. When using the RO fence to protect an AES-128 cryptographic module, we recovered all the bytes of the secret key with one million sensor traces, on average. In comparison, when using our novel wire fence, more than six million traces (an improvement of at least 6×) were required to recover all the bits of the secret key.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121858770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Reliability-aware Environment for Design Exploration for GPU Devices 面向GPU设备设计探索的可靠性感知环境

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139643

Robert Limas Sierra, Juan-David Guerrero-Balaguera, J. E. R. Condia, M. Reorda

{"title":"A Reliability-aware Environment for Design Exploration for GPU Devices","authors":"Robert Limas Sierra, Juan-David Guerrero-Balaguera, J. E. R. Condia, M. Reorda","doi":"10.1109/DDECS57882.2023.10139643","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139643","url":null,"abstract":"1 Nowadays, GPU platforms have gained wide importance in applications that require high processing power. Unfortunately, the advanced semiconductor technologies used for their manufacturing are prone to different types of faults. Hence, solutions are required to support the exploration of the resilience to faults of different architectures. Based on this motivation, this work presents an environment dedicated to the analysis of the impact of permanent faults on GPU platforms. This environment is based on GPGPU-Sim, with the objective of exploiting the configuration features of this tool and, thus, analyzing the effects of faults when changing the target architecture. To validate the environment and show its usability, a fault campaign has been carried out where three different GPU architectures (Kepler, Volta, and Turing) were used. In addition, each GPU has been modified with an arbitrary number of parallel processing cores (or SMs). Three representative applications (Vector Add, Scalar Product, and Matrix Multiply) were executed on each GPU, and the behavior of each architecture in the presence of permanent faults in the functional (i.e., integer unit and floating-point) units was analyzed. This fault campaign shows the usability of the environment and demonstrates its potential use to support decisions on the best architectural parameters for a given application.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124774131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

High-Throughput Approximate Multiplication Models in PyTorch PyTorch中的高通量近似乘法模型

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139366

Elias Trommer, Bernd Waschneck, Akash Kumar

引用次数: 0

Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial) 由机器学习模型驱动的硬件加速器近似值:(嵌入式教程)

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139484

Vojtěch Mrázek

引用次数: 0

A Low-Cost Combinational Approximate Multiplier 一种低成本组合近似乘法器

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139501

Z. Hojati, Z. Navabi

引用次数: 0

A Lightweight Intrusion Detection System against IoT Memory Corruption Attacks 针对物联网内存损坏攻击的轻量级入侵检测系统

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139718

Mohamed El Bouazzati, R. Tessier, P. Tanguy, G. Gogniat

引用次数: 0

Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults 对现场故障的具有延迟故障的汽车soc，通过逻辑BIST的二分类搜索来收集诊断信息

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2023-05-03 DOI: 10.1109/DDECS57882.2023.10139670

P. Bernardi, Gabriele Filipponi, M. Reorda, D. Appello, C. Bertani, V. Tancorre

{"title":"Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults","authors":"P. Bernardi, Gabriele Filipponi, M. Reorda, D. Appello, C. Bertani, V. Tancorre","doi":"10.1109/DDECS57882.2023.10139670","DOIUrl":"https://doi.org/10.1109/DDECS57882.2023.10139670","url":null,"abstract":"Embedded nano-electronic devices have spread in daily life over the past ten years. Chip and embedded system manufacturing has thus become more challenging in recent years.When safety-critical sectors like the automobile are considered, addressing system anomalies and faults is crucial. Therefore, it is necessary to develop and research innovative ways to maintain high reliability in safety-critical sectors despite the complexity of present Systems-on-Chip (SoCs).In order to ensure high reliability, and be compliant with reliability standards, designers started to add additional circuitry to perform on-device tests. Built-In-Self-Test (BIST) is a technology that allows to conduct exhaustive tests within devices and, most importantly, without the need for external equipment. BIST can detect faults by outputting a signature at test end, which can be compared with a known value. Thus such known signatures are key, and in case of a signature mismatch it is not trivial to understand the root cause of the failure.This paper proposes a methodology to find the first failing pattern which causes the BIST’s signature to deviate and a way to collect good signatures from in-field devices, at key on/off, where BISTs are programmed and executed by the firmware at maximum frequency for an industrial case study produced by STMicroelectronics.The transition delay fault model is the primary target for the described work.","PeriodicalId":220690,"journal":{"name":"2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129829901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0