对现场故障的具有延迟故障的汽车soc,通过逻辑BIST的二分类搜索来收集诊断信息

P. Bernardi, Gabriele Filipponi, M. Reorda, D. Appello, C. Bertani, V. Tancorre
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引用次数: 0

摘要

近十年来,嵌入式纳米电子器件在日常生活中得到了广泛应用。因此,近年来芯片和嵌入式系统制造变得更具挑战性。当考虑到像汽车这样的安全关键部门时,解决系统异常和故障至关重要。因此,有必要开发和研究创新的方法,以保持高可靠性的安全关键部门,尽管目前的系统芯片(soc)的复杂性。为了确保高可靠性,并符合可靠性标准,设计人员开始添加额外的电路来执行设备上的测试。内置自检(BIST)是一种允许在设备内进行详尽测试的技术,最重要的是,不需要外部设备。BIST可以通过在测试端输出签名来检测故障,该签名可以与已知值进行比较。因此,这些已知签名是关键,在签名不匹配的情况下,了解故障的根本原因并非易事。本文提出了一种方法来查找导致BIST签名偏离的第一个失败模式,以及一种从现场设备收集良好签名的方法,在键开/关时,BIST由固件以最高频率编程和执行,用于意法半导体生产的工业案例研究。转换延迟故障模型是本文工作的主要目标。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults
Embedded nano-electronic devices have spread in daily life over the past ten years. Chip and embedded system manufacturing has thus become more challenging in recent years.When safety-critical sectors like the automobile are considered, addressing system anomalies and faults is crucial. Therefore, it is necessary to develop and research innovative ways to maintain high reliability in safety-critical sectors despite the complexity of present Systems-on-Chip (SoCs).In order to ensure high reliability, and be compliant with reliability standards, designers started to add additional circuitry to perform on-device tests. Built-In-Self-Test (BIST) is a technology that allows to conduct exhaustive tests within devices and, most importantly, without the need for external equipment. BIST can detect faults by outputting a signature at test end, which can be compared with a known value. Thus such known signatures are key, and in case of a signature mismatch it is not trivial to understand the root cause of the failure.This paper proposes a methodology to find the first failing pattern which causes the BIST’s signature to deviate and a way to collect good signatures from in-field devices, at key on/off, where BISTs are programmed and executed by the firmware at maximum frequency for an industrial case study produced by STMicroelectronics.The transition delay fault model is the primary target for the described work.
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