Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques

Abstract

Nowadays, the manufacturing of Integrated Circuits (ICs) is highly distributed over different foundries yielding untrustworthy supply chains. This circumstance leads to concerns regarding the security, privacy, and reliability of the fabricated ICs, e.g., malicious usage and counterfeiting. Logic Locking (LL) is a prominent protection technique to safeguard against such concerns. Recently, the emerging technology of Reconfigurable Field-Effect Transistors (RFETs) has been utilized to implement new mechanisms based on Polymorphic Logic Gates (PLGs) to protect Intellectual Property (IP). The mechanisms’ assessment is indispensable to reinforce the newly introduced logic obfuscation and, hence, avoid any security breaches. So far, formal SAT-based and approximate Hamming Distance (HD)-based assessment techniques have been used for determining the protection quality. While the approximate and formal approaches can detect many security threats [1], they are still unable to detect optimization-based attacks. This work proposes a novel formal approach based on Pseudo Boolean Optimization (PBO) to assess the quality of LL structures for sequential circuits, enabling the detection of currently unconsidered security breaches. In particular, the proposed approach leverages formal techniques to analyze the key and state space of a sequential circuit to evaluate the security against optimization-based attacks. The experimental evaluation validates that the proposed scheme unveils weaknesses of the protection structure, which remain undetected when using existing techniques.