Supporting analog design for reliability by efficient provision of reliability information to designers

Abstract

Multiple degradation mechanisms limit the lifetime of integrated circuits (ICs). Different aspects can be tackled with Design for Reliability approaches already during circuit design to avoid serious implications of degradation for ICs in the field. For example, aging simulations can be performed to investigate the impact of the degradation of integrated transistors onto circuit performance. Since these simulations cause a significant verification effort, we work on approaches to efficiently feed reliability information back to circuit designers. This article discusses these approaches with their application scenarios and benefits.