{"title":"Junction termination extension (JTE), A new technique for increasing avalanche breakdown voltage and controlling surface electric fields in P-N junctions","authors":"V. Temple","doi":"10.1109/IEDM.1977.189277","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189277","url":null,"abstract":"Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions using an ion implanted junction extension for precise control of the depletion region charge in the junction termination. Theory is presented which shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages better than 95% of the ideal and at lower leakage current than the corresponding unimplanted devices. For example, diodes with a normal breakdown voltage of 1050 volts with a .5ma leakage current become 1400 volt (1450 ideal) devices with a 5µa leakage current. Applications of the technique are feasible in MOS technology, as would be expected, but are even more attractive in power devices in which the dramatically reduced surface fields are just as important as the extremely high breakdown voltages since it means more flexibility in passivation techniques, two of which we have used to date. Our results have also shown that the implant can be at a variety of temperatures with a good degree of success, extra process flexibility being the goal of these tests.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133177999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electrophysical properties of the germanium MIS-transistor","authors":"K. Z. Don, I. Neizvestny, V. N. Ovsyuk","doi":"10.1109/IEDM.1977.189334","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189334","url":null,"abstract":"The characteristics and interface properties of n-channel and p-channel Ge-IGFET's are investigated. Transistors were fabricated using Ge-SiO<inf>2</inf>-Si<inf>3</inf>N<inf>4</inf>structure. This structure is stable to a thermofield stress and has a low density of interface states (N<inf>ss</inf>∼10<sup>12</sup>cm<sup>-2</sup>eV<sup>-1</sup>). The experimental Ge-IGFET characteristics measured at BOOK and 77K are presented and compared with theory. The strong influence of the reverse bias between the channel and the substrate on the effective mobility of carriers in the channel are reported. This effect is due to decreasing of the carrier drift mobility in the channel rather than to the change of the interface states charge. The data of the investigations of Ge-IGFET in weak inversion are presented. The spectrum of interface states N<inf>ss</inf>(E) is determined. This spectrum is exponential and is approximated by N<inf>ss</inf>(E) = 10<sup>12</sup>exp[12(E-E<inf>o</inf>)] cm<sup>-2</sup>eV<sup>-1</sup>in energy range 0.17eV < E < 0.3 eV, where E<inf>o</inf>= 0.17 eV, and coincides with spectrum obtained from the temperature dependence of the threshold voltage measurements.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115567391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Boron monophosphide on Si and device applications","authors":"K. Shohno, H. Otake","doi":"10.1109/IEDM.1977.189298","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189298","url":null,"abstract":"n- or p-type boron monophosphide (BP) with a forbidden energy gap of 2.0 eV was epitaxially grown on Si substrates using a B2H6-PH3-H2system, n-type (phosphorous) or p-type (boron) diffusion layers were also formed in the Si substrates. By combining the conductivity type of the BP, the diffusion layer and the Si substrate, several types of BP-Si junctions were realized. Two examples of applied devices were a wide gap window solar cell (η = 8.3%) and a wide gap emitter transistor (β = 16). The focus of our research projects on BP is the development of III-V compound semiconductor technology along the lines of the Si planar process.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122117691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low RF loss metal-ceramic bonds","authors":"R. Russell, O. Doehler","doi":"10.1109/IEDM.1977.189285","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189285","url":null,"abstract":"Metal-ceramic interfaces in RF circuits of high power microwave tubes can be the source of attenuation, a heat barrier, and lead to thermal failure. Process improvements, leading to a reliable technique for applying Ti-Mo-Cu thin films that have low losses, close dimensional tolerence and high heat transfer, have been optimized over previously reported works. Sputter metallization of beryllia and subsequent diffusion brazing to copper comprise the basic process. Long range failures have been eliminated through strict control of the titanium layer thickness to 250Å. Bond strengths to the order of beryllia's yield stress of 12000 lbf/in2are achievable.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124601584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The buried-source VMOS dynamic RAM device","authors":"J. Barnes, S. Shabde, F. Jenne","doi":"10.1109/IEDM.1977.189230","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189230","url":null,"abstract":"The buried-source dynamic RAM device combines VMOS technology with the 1-transistor cell for a high performance and high density memory (1). This paper presents results of both experimental and theoretical analyses of the device as they apply to use in a 16K or 64K-bit dynamic RAM. The VMOST threshold voltage, breakdown voltage, weak inversion current, junction leakage current, and junction capacitance for both the forward and reverse mode of operation (reversal of source and drain) are experimentally related to the shape of the doping profile throughout the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. Finally, cell refresh data is presented that proves the operation of the device as a dynamic memory element.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128354202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Fukunaga, M. Kyomasu, A. Yasuoka, Y. Nakao, M. Nakayama
{"title":"FA-CMOS process for low power PROM with low avalanche injection voltage","authors":"S. Fukunaga, M. Kyomasu, A. Yasuoka, Y. Nakao, M. Nakayama","doi":"10.1109/IEDM.1977.189234","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189234","url":null,"abstract":"The combination of FAMOS and CMOS processes produces a new PROM with high performance and low power. This combined process named FA-CMOS will be described. The FA-CMOS process is based on the conventional silicon gate CMOS process using the selective oxidation process (SOP) technology. It is necessary to form the avalanche injection region capable of programming with low voltage without the breakdown of N+P-junction ( N+diffusion to P-well region ). Arsenic ions are implanted to form this region and the avalanche injection voltages of less than 20 V are obtained. In addition to the above mentioned process, the double diffusion technology simplifies the formation of source-drain and isolation region. Extremely low power ( 0.6 µW/bit ) PROM was successfully fabricated using the FA-CMOS process.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132145785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High performance output Schottky I2L/MTL","authors":"J. M. Herman","doi":"10.1109/IEDM.1977.189226","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189226","url":null,"abstract":"The design and characterization of a second generation I<sup>2</sup>L/MTL gate with five decoupled collectors, each collector incorporating a PtSi Schottky diode, is presented. A deep buried-collector implant is used to minimize base current losses and increase the effective up gain. An increase in A.C. performance by 40 to 70% over the second generation gate with N<sup>+</sup>collectors is obtained which depends on the effective Schottky barrier height or logic swing in the region of extrinsic delay. For an effective Schottky barrier height of 0.65 eV, the gate is fully functional over the military temperature range of -55 to 125°C where β<sup>eff</sup><inf>u</inf>≥ 4 and τ<sup>-</sup>d = 10 ns at 100 µA injector current. At 25°C the speed power product is constant for low injector currents at 0.16 pJ and increases to 0.7 pJ at 100 µA injector current.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131348275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High voltage dielectric isolation SCR integrated circuit process","authors":"J. D. Beasom","doi":"10.1109/IEDM.1977.189198","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189198","url":null,"abstract":"High voltage integrated circuit SCR's are required for applications such as cross point switching in telephone networks. This paper describes a process which produces these components in integrated form using dielectric isolation to eliminate substrate current, isolation leakage and latch-up and to achieve improved packing density. Significant characteristics of the devices produced are: breakover voltage > 250V; VF< 1.6v at anode current density = 100ma/mil2; anode current >1mA per mil2of chip area; ron< 10 ohms; gate turn off by cathode gate. Analysis and experimental results of two effects unique to dielectric isolation will be presented. One is confinement of minority carriers in a limited volume by the impenetrable oxide isolation. The other is the effect on breakdown voltage bf spreading a depletion layer through a lightly doped region and against oxide isolation and the variation of this voltage with bias on the poly silicon substrate.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125563905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"X-Band TWT with high efficiency and high PRF capability","authors":"K.A. Estrella, J. A. Alvarez","doi":"10.1109/IEDM.1977.189255","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189255","url":null,"abstract":"A gridded, PPM-focused, X-band, coupled cavity TWT with a midband efficiency of 49% has been successfully developed. This tube, designated the 8741H, provides a minimum output power of 4 kilowatts peak and 1 kilowatt average over a 300 MHz band and operates reliably at a PRF of greater than 200 KHz. The requirements for high efficiency and high PRF operation dictated the selection of the of the design parameters of this liquid-cooled, air-borne TWT. These features are discussed in further detail in this paper.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121674944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On measurement of surface impurity profiles of laterally diffused regions","authors":"J. Sansbury, J. Moll, Hee-Gook Lee","doi":"10.1109/IEDM.1977.189300","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189300","url":null,"abstract":"A better understanding for two-dimensional diffused profiles becomes crucial with the trend toward smaller device geometries. However, little experimental data has been available. This paper describes an experiment which extracts the surface impurity profiles near the mask edges from the inversion characteristics of nonuniformly doped surface regions. Test structures for this purpose have been fabricated with a CMOS process. An algo rithm has been developed to extract the surface doping profile in the laterally diffused regions from the IDvs. VGcharacteristics of these devices, The measured profiles are in good agreement with a first-order two-dimensional diffusion model.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131778090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}