{"title":"埋源VMOS动态RAM器件","authors":"J. Barnes, S. Shabde, F. Jenne","doi":"10.1109/IEDM.1977.189230","DOIUrl":null,"url":null,"abstract":"The buried-source dynamic RAM device combines VMOS technology with the 1-transistor cell for a high performance and high density memory (1). This paper presents results of both experimental and theoretical analyses of the device as they apply to use in a 16K or 64K-bit dynamic RAM. The VMOST threshold voltage, breakdown voltage, weak inversion current, junction leakage current, and junction capacitance for both the forward and reverse mode of operation (reversal of source and drain) are experimentally related to the shape of the doping profile throughout the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. Finally, cell refresh data is presented that proves the operation of the device as a dynamic memory element.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"The buried-source VMOS dynamic RAM device\",\"authors\":\"J. Barnes, S. Shabde, F. Jenne\",\"doi\":\"10.1109/IEDM.1977.189230\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The buried-source dynamic RAM device combines VMOS technology with the 1-transistor cell for a high performance and high density memory (1). This paper presents results of both experimental and theoretical analyses of the device as they apply to use in a 16K or 64K-bit dynamic RAM. The VMOST threshold voltage, breakdown voltage, weak inversion current, junction leakage current, and junction capacitance for both the forward and reverse mode of operation (reversal of source and drain) are experimentally related to the shape of the doping profile throughout the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. Finally, cell refresh data is presented that proves the operation of the device as a dynamic memory element.\",\"PeriodicalId\":218912,\"journal\":{\"name\":\"1977 International Electron Devices Meeting\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1977 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1977.189230\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1977.189230","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The buried-source dynamic RAM device combines VMOS technology with the 1-transistor cell for a high performance and high density memory (1). This paper presents results of both experimental and theoretical analyses of the device as they apply to use in a 16K or 64K-bit dynamic RAM. The VMOST threshold voltage, breakdown voltage, weak inversion current, junction leakage current, and junction capacitance for both the forward and reverse mode of operation (reversal of source and drain) are experimentally related to the shape of the doping profile throughout the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. Finally, cell refresh data is presented that proves the operation of the device as a dynamic memory element.
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