2019 22nd Euromicro Conference on Digital System Design (DSD)最新文献_第8页

Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems 自适应多处理系统中基于sram的低成本SEU监视器设计

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00080

Junchao Chen, M. Andjelković, A. Simevski, Yuanqing Li, Patryk Skoncej, M. Krstic

引用次数: 13

Online Peak Power and Maximum Temperature Management in Multi-core Mixed-Criticality Embedded Systems 多核混合临界嵌入式系统的在线峰值功率和最高温度管理

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00084

Behnaz Ranjbar, T. D. A. Nguyen, A. Ejlali, Akash Kumar

{"title":"Online Peak Power and Maximum Temperature Management in Multi-core Mixed-Criticality Embedded Systems","authors":"Behnaz Ranjbar, T. D. A. Nguyen, A. Ejlali, Akash Kumar","doi":"10.1109/DSD.2019.00084","DOIUrl":"https://doi.org/10.1109/DSD.2019.00084","url":null,"abstract":"In this work, we address peak power and maximum temperature in multi-core Mixed-Criticality (MC) systems. In these systems, a rise in peak power consumption may generate more heat beyond the cooling capacity. Additionally, the reliability and timeliness of MC systems may be affected due to excessive temperature. Therefore, managing peak power consumption has become imperative in multi-core MC systems. In this regard, we propose an online peak power management heuristic for multi-core MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and Dynamic Voltage and Frequency Scaling (DVFS). Specifically, our approach examines multiple tasks ahead to determine the most appropriate one for slack assignment instead of just one task as in the literature. The selection is based on the impact of the tasks on peak power and temperature of the system. The DVFS is then applied to that task to reduce the system peak power and maximum temperature. Further, a re-mapping technique is proposed to further improve the results. Our experimental results show that our heuristic achieves up to 18.2% reduction in system peak power consumption and 8.1% reduction in maximum temperature compared to an existing method. The inherent energy consumption is also reduced by up to 50%.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125999501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

CMOS Illumination Discloses Processed Data CMOS照明公开处理数据

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00062

Jan Belohoubek, P. Fiser, Jan Schmidt

引用次数: 2

A Very Compact Architecture of CLEFIA Block Cipher for Secure IoT Systems 用于安全物联网系统的CLEFIA分组密码的非常紧凑的架构

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00097

L. Pyrgas, P. Kitsos

引用次数: 5

Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation 用批并行逻辑评估改进数字电路仿真

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00031

Maria Patrou, Jean-Philippe Legault, Aaron Graham, K. Kent

{"title":"Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation","authors":"Maria Patrou, Jean-Philippe Legault, Aaron Graham, K. Kent","doi":"10.1109/DSD.2019.00031","DOIUrl":"https://doi.org/10.1109/DSD.2019.00031","url":null,"abstract":"Integrated circuit simulators reproduce the behavior and functionality of the underlying circuits. They are part of FPGA CAD flow tools and they ensure the correctness of the circuits after the various conversions and optimizations occurring in the previous stages. During this procedure a graph with dependencies across nodes is created for each circuit design. Large circuits, and thus graphs, require more time to be simulated, making a parallel approach necessary. We explore a new solution-batch-parallel simulation in which the circuit output is calculated by worker threads that process batches of input vectors. The threads traverse and calculate their assigned nodes in parallel taking into consideration the intra-node dependencies. Furthermore, a node calculation analysis is performed and used to achieve work balance across threads. We apply this technique on the open-source Odin II framework and compare it with the existing approaches. The batch-parallel simulation is compared with the two existing approaches, single-threaded and multi-threaded, under various configurations, considering the number of threads and the batch sizes. The results demonstrate performance gains against the existing approaches in the majority of the benchmarks used for specific metrics, such as simulation elapsed time.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123186924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design and Implementation of a Low-Power, Embedded CNN Accelerator on a Low-end FPGA 低功耗嵌入式CNN加速器在低端FPGA上的设计与实现

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00102

Bahareh Khabbazan, S. Mirzakuchaki

引用次数: 20

Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model 基于systemverilog的Sigma-Delta ADC实数模型的设计

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00028

Constantina Tsechelidou, Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos

{"title":"Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model","authors":"Constantina Tsechelidou, Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos","doi":"10.1109/DSD.2019.00028","DOIUrl":"https://doi.org/10.1109/DSD.2019.00028","url":null,"abstract":"Mixed-signal applications constitute a significant trend in the semiconductor industry. Huge effort is focused on creating fast and accurate mixed-signal designs, which include both analog and digital parts. A widely used mixed-signal circuit in modern electronics is the Sigma-Delta analog-to-digital converter (ADC). Sigma-Delta modulation is mainly exploited as a method for encoding analog signals into digital signals as found in an ADC. Apart from that, it is used to convert high bit-count, low-frequency digital signals into lower bit-count, higherfrequency digital signals as part of the process to convert digital signals into analog as part of a digital-to-analog converter (DAC). In this work, a first-order Sigma-Delta ADC real number model using SystemVerilog is presented, in order to greatly improve simulation efficiency while keeping accuracy in a satisfying level. The proposed sigma-delta ADC real number model consists of a sigma-delta modulator, a digital filter and a decimator. The design and simulation of the proposed Sigma-Delta ADC model was accomplished using the Cadence Incisive Enterprise Simulator. Moreover, the proposed model is compared to a Verilog-AMS Sigma-Delta ADC, having its design implemented and simulated in Cadence Virtuoso and Spectre AMS Designer. In all test cases, the presented SystemVerilog-based real number model displays high simulation time gains, along with acceptable accuracy.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"38 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132939945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

PAIG Rewriting: The Way to Scalable Multifunctional Digital Circuits Synthesis pag改写:可扩展多功能数字电路合成方法

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00056

Adam Crha, Václav Simek, R. Ruzicka

引用次数: 4

Framework of Key Enabling Technologies for Safe and Autonomous Drones' Applications 安全和自主无人机应用的关键使能技术框架

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00067

R. Nouacer, H. E. Ortiz, Yassine Ouhammou, R. González

{"title":"Framework of Key Enabling Technologies for Safe and Autonomous Drones' Applications","authors":"R. Nouacer, H. E. Ortiz, Yassine Ouhammou, R. González","doi":"10.1109/DSD.2019.00067","DOIUrl":"https://doi.org/10.1109/DSD.2019.00067","url":null,"abstract":"The potential applications for drones, especially those in manned areas or into non-segregated airspace, are currently not possible without the development and validation of certain key enabling technologies: \"detect and avoid\", \"air traffic management\" and \"command and control (C2) link\". SESAR JU identified that issue has a high impact on European innovation, which demands R&D investments and incentives for the convergence of shared technologies and markets. The COMP4DRONES project complements SESAR JU efforts with a particular focus on safe software and hardware drone architectures. COMP4DRONES will bear a holistically designed ecosystem ranging from application to electronic components. The ecosystem aims at supporting (1) efficient customization and incremental assurance of drone-embedded platforms, (2) safe autonomous decision making concerning individual or cooperative missions, (3) trustworthy drone-to-drone and drone-to-ground communications even in presence of malicious attackers and under the intrinsic platform constraints, and (4) agile and cost-effective design and assurance of drone modules and systems. Lead applications driving ecosystem development and benchmarking on the fields of transport, inspection, logistic, precision agriculture, parcel delivery, among others, will be produced.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123061435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Analyzing the Impact of Secure CAN Networks on Braking Dynamics of Cooperative Driving 安全CAN网络对协同驾驶制动动力学的影响分析

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00104

Dharshan Krishna Murthy, Mingqing Zhang, Alejandro Masrur

引用次数: 0