2019 22nd Euromicro Conference on Digital System Design (DSD)最新文献_第10页

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2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/dsd.2019.00002

引用次数: 0

Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops 基于标准单元的TMR触发器辐射硬度时序建模研究

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00100

O. Schrape, A. Breitenreiter, Steffen Zeidler, M. Krstic

引用次数: 3

Analyzing the Impact of Probabilistic Estimates on Communication Reliability at Intelligent Crossroads 概率估计对智能十字路口通信可靠性的影响分析

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00039

Daniel Markert, Philip Parsch, Alejandro Masrur

{"title":"Analyzing the Impact of Probabilistic Estimates on Communication Reliability at Intelligent Crossroads","authors":"Daniel Markert, Philip Parsch, Alejandro Masrur","doi":"10.1109/DSD.2019.00039","DOIUrl":"https://doi.org/10.1109/DSD.2019.00039","url":null,"abstract":"Intelligent crossroads aim to substitute conventional traffic lights by coordinating the order in which vehicles cross an intersection. Since vehicles come and go at arbitrary points in time, this results in an open-ended setting that is difficult to analyze with deterministic methods. In particular, deterministic methods fail to provide meaningful estimates of the maximum number of vehicles at the intersection, which is paramount to assess communication reliability and, in the end, guarantee safety. In contrast, statistical and probabilistic techniques are more suitable for this purpose and constitute the focus of this paper. We especially investigate how different driving directions and vehicle lengths influence the quality of probabilistic estimates in approximating the maximum number of vehicles at the intersection. These estimates are then incorporated into the design and analysis of the crossroad VANET to derive guarantees on communication reliability. Our results show that such estimates can greatly reduce pessimism and overdesign compared to deterministic approaches. These and other benefits are illustrated by means of a detailed case study and simulationsusing OMNeT++.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124222230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Real-Time Textureless-Region Tolerant High-Resolution Depth Estimation System 实时无纹理区域容忍高分辨率深度估计系统

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00020

Bilal Demir, J. Thiran, Y. Leblebici

引用次数: 0

A Survey on Multi-unmanned Aerial Vehicle Communications for Autonomous Inspections 面向自主检测的多无人机通信研究进展

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00088

Liping Shi, N. J. H. Marcano, R. Jacobsen

引用次数: 12

Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards 智能电子锁的可靠性测试:分析与初步研究

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00079

Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, R. Panek, Martin Krcma, Z. Kotásek

{"title":"Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards","authors":"Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, R. Panek, Martin Krcma, Z. Kotásek","doi":"10.1109/DSD.2019.00079","DOIUrl":"https://doi.org/10.1109/DSD.2019.00079","url":null,"abstract":"This research paper presents an analysis of electronic smart locks and explores the influences of faults on its controller unit. Electronic smart locks often utilize stepper motor as an actuator. Stepper motors, however, need a controller, which is usually implemented in a processor. The aim of our research is to examine the consequences of a failing controller processor. In our previous research, we developed a platform for fault tolerance testing with the ability to monitor the impacts on the mechanical part. We also developed a framework for accelerated testing of fault tolerance properties. The processor can be implemented in an FPGA (Field Programmable Gate Array) in order to be able to emulate HW faults inside the processor. In this paper, the concept of testing a smart lock is presented alongside with the first experimental results utilizing the direct generation of invalid stimuli for the stepper motor. In our research, we found out that random errors probably could not be used for an unauthorized unlock, especially if the lock utilizes a mechanical gearbox. Deeper logic and knowledge of the correct sequence of steps used by the selected motor are needed to perform an attack to unlock the lock. On the other hand, random sequences could cause that lock not to be locked by falsifying the lock request sequence. The second interesting fact is that x% of faults in the valid sequence give the same rotation angle as (100-x)% of faults.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An IoT-Based Framework for Elderly Remote Monitoring 基于物联网的老年人远程监测框架

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00070

Issam Boukhennoufa, A. Amira, F. Bensaali, D. Anagnostopoulos, M. Nikolaidou, Christos Kotronis, Elena Politis, G. Dimitrakopoulos

{"title":"An IoT-Based Framework for Elderly Remote Monitoring","authors":"Issam Boukhennoufa, A. Amira, F. Bensaali, D. Anagnostopoulos, M. Nikolaidou, Christos Kotronis, Elena Politis, G. Dimitrakopoulos","doi":"10.1109/DSD.2019.00070","DOIUrl":"https://doi.org/10.1109/DSD.2019.00070","url":null,"abstract":"This Paper presents an Internet of Things (IoT) based framework to monitor ECG for biometric recognition and acceleration for fall detection. To this end, an-IoT based Remote Elderly Monitoring System (REMS) platform is described. REMS consists of a Shimmer3TM device transmitting physiological signal wirelessly to a nearby gateway which routes the data to a remote IoT-platform, able to accommodate dynamically changing configurations. The Shimmer firmware has been modified to send data based on the compressive sensing theory in order to ameliorate energy consumption in addition of real data, and the analysis and processing are done locally on a heterogeneous multicore edge device in order to solve latency issues related to cloud reliance. Subsequently the framework has been designed to handle the different parameter settings and multiple scenarios in a user-friendly way. Furthermore, it allows the user to monitor physiological data and acquire some feedback related to their analysis. Depending on a scenario (energy save, secure communication) the system can be configured manually or automatically to monitor ECG or acceleration data and displays them, it can also identify the subject based on ECG recognition and detect fall if it occurs.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"20 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120837430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Reconfigurable Architecture for Posit Arithmetic 位算术的可重构结构

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00022

Souradip Sarkar, Purushotham Murugappa, M. Gomony

{"title":"A Reconfigurable Architecture for Posit Arithmetic","authors":"Souradip Sarkar, Purushotham Murugappa, M. Gomony","doi":"10.1109/DSD.2019.00022","DOIUrl":"https://doi.org/10.1109/DSD.2019.00022","url":null,"abstract":"Physical layer of modern communication systems involves several floating point computations that require higher numerical fidelity and dynamic range for achieving the maximum data rate. Posit number format is a promising alternative for floating point computation as it provides a better dynamic range and numerical fidelity for the same number of bits used for representation. However, the Posit number format has not yet been thoroughly studied in the context of signal processing algorithms in the physical layer. In addition, a configurable Posit arithmetic hardware is essential for adapting to the ever changing communication standards and to configure the dynamic range according to algorithmic demands. The main contributions in this paper are: 1) Performance analysis of common signal processing algorithms using the Posit number format in comparison with the IEEE Standard for Single Precision Floating Point arithmetic (IEEE 754). 2) A novel reconfigurable hardware accelerator for Posit arithmetic operations and comparison with the state-of-the-art Posit and IEEE Floating Point arithmetic architectures. Although our proposed architecture consumes over 3X energy and area compared to IEEE Single Precision arithmetic, our results show that using the Posit number format for physical layer algorithms results in significant performance gain. We achieved over 15 dB and 25 dB gain for FFT and matrix multiplication algorithms. In addition, compared to state-of-the-art Posit arithmetic architecture, our proposed architecture resulted in over 2X speedup in operating frequency and 35% savings in energy consumption.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124365180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Model-Based Processor-in-the-Loop Framework for Composable Multi-core Platforms 基于模型的可组合多核平台处理器在环框架

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00090

Mojtaba Haghi, Martijn Koedam, Dip Goswami, K. Goossens

引用次数: 1

Application Study of Hardware-Based Security for Future Industrial IoT 未来工业物联网硬件安全应用研究

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00044

R. Matischek, Benjamin Bara

引用次数: 4