2019 22nd Euromicro Conference on Digital System Design (DSD)最新文献_第9页

GPU4S: Embedded GPUs in Space GPU4S:空间嵌入式gpu

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00064

Leonidas Kosmidis, J. Lachaize, J. Abella, O. Notebaert, F. Cazorla, D. Steenari

{"title":"GPU4S: Embedded GPUs in Space","authors":"Leonidas Kosmidis, J. Lachaize, J. Abella, O. Notebaert, F. Cazorla, D. Steenari","doi":"10.1109/DSD.2019.00064","DOIUrl":"https://doi.org/10.1109/DSD.2019.00064","url":null,"abstract":"Following the same trend of automotive and avionics, the space domain is witnessing an increase in the on-board computing performance demands. This raise in performance needs comes from both control and payload parts of the spacecraft and calls for advanced electronics able to provide high computational power under the constraints of the harsh space environment. On the non-technical side, for strategic reasons it is mandatory to get European independence on the used computing technology. In this project, which is still in its early phases, we study the applicability of embedded GPUs in space, which have shown a dramatic improvement of their performance per-watt ratio coming from their proliferation in consumer markets based on competitive European technology. To that end, we perform an analysis of the existing space application domains to identify which software domains can benefit from their use. Moreover, we survey the embedded GPU domain in order to assess whether embedded GPUs can provide the required computational power and identify the challenges which need to be addressed for their adoption in space. In this paper, we describe the steps to be followed in the project, as well as the results of our preliminary analyses in the first months of the project.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131362747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

PRYSTINE - Technical Progress After Year 1 PRYSTINE -第一年之后的技术进步

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00063

N. Druml, O. Veledar, Georg Macher, G. Stettinger, Selim Solmaz, Jakob Reckenzaun, S. Diaz, M. Marcano, J. Villagrá, R. Beekelaar, Johannes Jany-Luig, Marta Maria Corredoira, P. Burgio, Christian Ballato, B. Debaillie, Lars van Meurs, A. Terechko, F. Tango, A. Ryabokon, A. Anghel, O. Icoglu, Sumeet S. Kumar, G. Dimitrakopoulos

引用次数: 5

Odyn: Deadlock Prevention and Hybrid Scheduling Algorithm for Real-Time Dataflow Applications Odyn:实时数据流应用的死锁预防和混合调度算法

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00023

Benjamin Dauphin, R. Pacalet, Andrea Enrici, L. Apvrille

{"title":"Odyn: Deadlock Prevention and Hybrid Scheduling Algorithm for Real-Time Dataflow Applications","authors":"Benjamin Dauphin, R. Pacalet, Andrea Enrici, L. Apvrille","doi":"10.1109/DSD.2019.00023","DOIUrl":"https://doi.org/10.1109/DSD.2019.00023","url":null,"abstract":"In recent wireless communication standards (4G, 5G), the growing need for dynamic adjustments of transmission parameters (e.g., modulation, bandwidth, channel coding rate) makes traditional static scheduling approaches less and less efficient. The reason being that precomputed fixed mapping and scheduling prevent the system from dynamically adapting to changes of the operating conditions (e.g. wireless channel quality, available bandwidth). In this paper, we present Odyn, a hybrid approach for the scheduling and memory management of periodic dataflow applications on parallel, heterogeneous, Non-Uniform Memory Architecture (NUMA) platforms. In Odyn, the ordering of tasks and memory allocation are distributed and computed simultaneously at run-time for each Processing Element. Odyn also proposes a mechanism to prevent deadlocks caused by attempts to allocate buffers in size-limited memories. This technique, based on the static computation of exclusion relations among buffers in a target application, removes the need for backtracking that is typical of dynamic scheduling algorithms. We demonstrate the effectiveness of Odyn on a testbench that simulates the interactions of randomly generated concurrent applications. We also demonstrate its deadlock prevention technique on a selection of use cases.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"96 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133984990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design and Implementation of a Fast and Scalable NTT-Based Polynomial Multiplier Architecture 基于ntt的快速可扩展多项式乘法器架构的设计与实现

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00045

A. Mert, Erdinç Öztürk, E. Savaş

{"title":"Design and Implementation of a Fast and Scalable NTT-Based Polynomial Multiplier Architecture","authors":"A. Mert, Erdinç Öztürk, E. Savaş","doi":"10.1109/DSD.2019.00045","DOIUrl":"https://doi.org/10.1109/DSD.2019.00045","url":null,"abstract":"In this paper, we present an optimized FPGA implementation of a novel, fast and highly parallelized NTT-based polynomial multiplier architecture, which proves to be effective as an accelerator for lattice-based homomorphic cryptographic schemes. As I/O operations are as time-consuming as NTT operations during homomorphic computations in a host processor/accelerator setting, instead of achieving the fastest NTT implementation possible on the target FPGA, we focus on a balanced time performance between the NTT and I/O operations. Even with this goal, we achieved the fastest NTT implementation in literature, to the best of our knowledge. For proof of concept, we utilize our architecture in a framework for Fan-Vercauteren (FV) homomorphic encryption scheme, utilizing a hardware/software co-design approach, in which polynomial multiplication operations are offloaded to the accelerator via PCIe bus while the rest of operations in the FV scheme are executed in software running on an off-the-shelf desktop computer. Specifically, our framework is optimized to accelerate Simple Encrypted Arithmetic Library (SEAL), developed by the Cryptography Research Group at Microsoft Research, for the FV encryption scheme, where large degree polynomial multiplications are utilized extensively. The hardware part of the proposed framework targets Xilinx Virtex-7 FPGA device and the proposed framework achieves almost 11x latency speedup for the offloaded operations compared to their pure software implementations. We achieved a throughput of almost 800K polynomial multiplications per second, for polynomials of degree 1024 with 32-bit coefficients.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"6 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131901206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

On the Bright Side of Darkness: Side-Channel Based Authentication Protocol Against Relay Attacks 黑暗的光明面:针对中继攻击的基于侧信道的认证协议

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00040

Guillaume Dabosville, Houssem Maghrebi, A. Lhuillery, J. Bringer, Thanh-Ha Le

引用次数: 2

The CASPER Project Approach Towards User-Centric Mobile Networks 以用户为中心的移动网络的CASPER项目方法

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00065

Eirini Liotou, D. Tsolkas, S. Tennina, L. Pomante, Giorgos Kalpaktsoglou, N. Passas

引用次数: 0

Circumventing Uniqueness of XOR Arbiter PUFs 规避XOR仲裁puf的唯一性

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00041

Caio Hoffman, C. Gebotys, Diego F. Aranha, M. Côrtes, G. Araújo

引用次数: 6

Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs 基于CMOS的近似计算非精确减除器的设计:与基于PTL设计的深入比较

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00034

C. Jha, Joycee Mekie

{"title":"Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs","authors":"C. Jha, Joycee Mekie","doi":"10.1109/DSD.2019.00034","DOIUrl":"https://doi.org/10.1109/DSD.2019.00034","url":null,"abstract":"Multimedia applications consume an immense amount of energy. These applications have division as one of the fundamental operations. Division is also one of the costliest operations in terms of energy consumption. Thus, various works have been done to address the issue of energy consumption in multimedia applications by using approximate dividers based on pass transistor logic (PTL). Since these applications have resilience towards erroneous computations huge energy benefits are obtained as a result of approximate computations with similar output quality. In this paper, we have shown that PTL based designs are not suitable for lower technology nodes. We performed an in-depth analysis using UMC 65nm and UMC 28nm to highlight the adverse effects of technology scaling on energy consumption and delay in PTL based design as compared to CMOS based designs. We also propose four different inexact CMOS subtractor (ICS) designs, as they are the basic repeated module in inexact restoring array dividers (IRADs). Our proposed ICS designs consume ~ 2× lesser dynamic energy, ~ 3× lesser static power and have ~ 2.5× lesser delay as compared to the existing PTL based designs in UMC 65nm. These benefits increase for UMC 28nm, which shows PTL based designs further worsens at lower technology nodes. IRADs also give about 50% reduction in energy consumption with only 3% degradation in Structural Similarity (SSIM) Index, an image quality metric in multimedia applications like change detection, background removal, and JPEG compression, as compared to exact restoring array divider (ERAD).","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133835849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A Study of Performance and Power Consumption Differences Among Different ISAs 不同isa的性能和功耗差异研究

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00098

Ayaz Akram, L. Sawalha

引用次数: 3

Enhancing Battery Pack Capacity Utilization in Electric Vehicle Fleets via SoC-Preconditioning 通过soc预处理提高电动汽车电池组容量利用率

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00059

Alexander Lamprecht, Ananth Garikapati, Swaminathan Narayanaswamy, S. Steinhorst

{"title":"Enhancing Battery Pack Capacity Utilization in Electric Vehicle Fleets via SoC-Preconditioning","authors":"Alexander Lamprecht, Ananth Garikapati, Swaminathan Narayanaswamy, S. Steinhorst","doi":"10.1109/DSD.2019.00059","DOIUrl":"https://doi.org/10.1109/DSD.2019.00059","url":null,"abstract":"Modern public transport solutions based on autonomous electric vehicles are on the rise. Public transportation as a service on demand is becoming a reality. Therefore, vehicles suitable for these kinds of applications need to be developed. One critical factor for such vehicles is a short turnaround time at the charging spot. Maximizing the utilization of a given battery pack capacity and minimizing the time spent charging are therefore of central importance. In this paper, we propose a novel preconditioning algorithm to minimize the time an EV is connected to the charging station. Our proposed approach uses existing Active Cell Balancing (ACB) hardware of the battery pack to precondition the State of Charge (SoC) of cells such that all cells reach the top SoC threshold at the same time without requiring an additional balancing phase during charging. This is done by considering the individual cells' charging rate to precondition them for achieving an equal time to full charge. Applying the same approach for discharging, we also extend the driving range of an EV, which otherwise is limited by the cell with the lowest SoC in the pack. Case studies show that our proposed preconditioning algorithm increases the usable energy of the battery pack by up to 3% compared to conventional balancing algorithms all while effectively halving the time connected to a charging station, all without requiring any additional hardware components.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120948890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1