A Very Compact Architecture of CLEFIA Block Cipher for Secure IoT Systems

In this paper, a very compact architecture of the CLEFIA block cipher is presented. This architecture has a 128-bit plaintext/ciphertext and a 128-bit key and processes the data using a 4-bit datapath and therefore requires only a small number of hardware resources. The target of this architecture is ultra-low area devices for Internet of Things systems. The design was coded using the Verilog language and the BASYS3 board (Artix 7 XC7A35T) was used for the hardware implementation. The proposed implementation utilizes only 606 FPGA LUTs and 477 FFs and reaches a data throughput of 28 Mbps at 115 MHz clock frequency.