2019 22nd Euromicro Conference on Digital System Design (DSD)最新文献_第7页

Side-Channel Attack on the A5/1 Stream Cipher A5/1流密码的侧信道攻击

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00099

M. Jureček, J. Bucek, R. Lórencz

引用次数: 9

HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions 考虑基于xtratum的软件分区的混合临界嵌入式系统软硬件协同设计框架

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00085

V. Muttillo, L. Pomante, Patricia Balbastre Betoret, José-Enrique Simó-Ten, A. Crespo

{"title":"HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions","authors":"V. Muttillo, L. Pomante, Patricia Balbastre Betoret, José-Enrique Simó-Ten, A. Crespo","doi":"10.1109/DSD.2019.00085","DOIUrl":"https://doi.org/10.1109/DSD.2019.00085","url":null,"abstract":"Heterogeneous parallel devices are becoming widely diffused in the embedded systems application field since they allow to improve time performances and other orthogonal metrics (e.g., cost, power, size, etc.) at the same time. In such a context, the introduction of safety requirements, as dictated by the relevant standards (i.e., DO-178 B/C and RTCA/DO-254 in airborne systems, ARINC 653 for avionics software, ISO-26262 in automotive domain, etc.) while considering shared resources on a heterogeneous parallel HW platform, adds further challenges to industrial and academic research. This kind of platforms that execute tasks with different levels of criticality are commonly called mixed-criticality embedded systems. So, the main problem in their management is to ensure that low criticality tasks do not interfere with high criticality ones. The final goal is to allow several applications to interact and coexist on the same platform. For this, the exploitation of virtualization technologies (i.e., hypervisors) allows to guarantee isolation and to satisfy certification requirements but introduces scheduling overhead and new HW/SW partitioning challenges. In such a scenario, this work focuses on a framework for modeling, analysis, and validation of mixed-criticality and real-time systems based on an existing \"Model-Based Electronic System Level HW/SW Co-Design\" methodology. The main contribution of this work is the integration of the considered framework with Xamber tool in order to provide systems implementations by exploiting a design space exploration able to consider Xtratum-based SW partitions.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130293972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller Takagi-Sugeno模糊控制器的可配置硬件加速器体系结构

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00024

O. Boncalo, A. Amaricai, Z. Lendek

引用次数: 3

An Efficient FPGA Implementation of Versatile Video Coding Intra Prediction 一种多功能视频编码内预测的高效FPGA实现

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00037

Hasan Azgin, Ercan Kalali, Ilker Hamzaoglu

引用次数: 5

MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems 微let:一种新的基于sdc的基于芯片系统的通信协议

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00019

Soultana Ellinidou, G. Sharma, Sotirios Kontogiannis, O. Markowitch, J. Dricot, G. Gogniat

{"title":"MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems","authors":"Soultana Ellinidou, G. Sharma, Sotirios Kontogiannis, O. Markowitch, J. Dricot, G. Gogniat","doi":"10.1109/DSD.2019.00019","DOIUrl":"https://doi.org/10.1109/DSD.2019.00019","url":null,"abstract":"Currently the industry moves to smaller process nodes even if the cost for yielding large dies continues to increase, moving to the 5nm and even 3nm nodes. Hence a chiplet-based design has been initiated and quickly gain attention from industry, academia and government agencies. This cutting edge approach became advantageous to break down a large die into smaller chiplets in order to improve yield and binning. In order to exploit this new approach the interconnect fabric connecting the nodes of the entire system should be of high importance to enable the properly distribution of the data. Each individual chiplet may contain its own local Network on Chip (NoC), which operates for intra-chiplet traffic. However the communication over chiplet-based systems is complicated enough, due to various routing algorithms and NoC topologies and an alternative solution is needed. In this paper we introduce an SDNoC(Software Define Network on Chip)-based communication protocol for chiplet-based systems, called MicroLET, which consists of a flexible and modular SDNoC architecture and 3 main phases: Handshake, Network Monitoring, Routing. An implementation of the SDNoC architecture and an evaluation of the proposed routing algorithm compared to the XY and the Odd-Even algorithms within different traffic scenarios is presented. Through the evaluation of the MicroLET protocol, it is proven that it could be a good candidate for the future chiplet-based systems.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123791262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Enabling Cognitive Autonomy on Small Drones by Efficient On-Board Embedded Computing: An ORB-SLAM2 Case Study 通过高效机载嵌入式计算实现小型无人机的认知自主:一个ORB-SLAM2案例研究

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00026

Erqian Tang, Sobhan Niknam, T. Stefanov

{"title":"Enabling Cognitive Autonomy on Small Drones by Efficient On-Board Embedded Computing: An ORB-SLAM2 Case Study","authors":"Erqian Tang, Sobhan Niknam, T. Stefanov","doi":"10.1109/DSD.2019.00026","DOIUrl":"https://doi.org/10.1109/DSD.2019.00026","url":null,"abstract":"In this paper, we present a case study which investigates whether/how Simultaneous Localization and Mapping (SLAM), e.g., the ORB-SLAM2 application, can be executed on a small, energy-efficient, multi-processor embedded platform with an ARM big.LITTLE architecture, e.g., the ODROID-XU4 platform, mounted on a small drone with a limited energy budget while meeting real-time performance requirements. More specifically, we model and implement ORB-SLAM2 as a Kahn Process Network (KPN) which exploits pipeline parallelism and enables efficient mapping and execution of ORB-SLAM2 onto ODROID-XU4. Moreover, our KPN model enables the application of generic model transformations to exploit data-level parallelism as well. Then, we propose and implement, on top of the Linux operating system, an environment for efficient execution of applications modeled as KPNs. Finally, we perform a simple design space exploration (DSE) to investigate the trade-off between system performance and power consumption when alternative ORB-SLAM2 KPNs are executed on different configurations of the ODROID-XU4 platform. The obtained results of this DSE clearly show the feasibility of running ORB-SLAM2 on ODROID-XU4 in real time with a limited power budget for a given range of flying time, thereby enabling cognitive autonomy on small drones.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125248946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Smart Chair System for Posture Correction 姿势矫正的智能椅子系统

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00069

George Flutur, Bogdan Movileanu, Lengyel Károly, I. Danci, Cosovanu Daniel, O. Stan

引用次数: 7

TOT-Net: An Endeavor Toward Optimizing Ternary Neural Networks TOT-Net:优化三元神经网络的努力

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00052

Najmeh Nazari, Mohammad Loni, M. Salehi, M. Daneshtalab, Mikael Sjödin

{"title":"TOT-Net: An Endeavor Toward Optimizing Ternary Neural Networks","authors":"Najmeh Nazari, Mohammad Loni, M. Salehi, M. Daneshtalab, Mikael Sjödin","doi":"10.1109/DSD.2019.00052","DOIUrl":"https://doi.org/10.1109/DSD.2019.00052","url":null,"abstract":"High computation demands and big memory resources are the major implementation challenges of Convolutional Neural Networks (CNNs) especially for low-power and resource-limited embedded devices. Many binarized neural networks are recently proposed to address these issues. Although they have significantly decreased computation and memory footprint, they have suffered from accuracy loss especially for large datasets. In this paper, we propose TOT-Net, a ternarized neural network with [-1, 0, 1] values for both weights and activation functions that has simultaneously achieved a higher level of accuracy and less computational load. In fact, first, TOT-Net introduces a simple bitwise logic for convolution computations to reduce the cost of multiply operations. To improve the accuracy, selecting proper activation function and learning rate are influential, but also difficult. As the second contribution, we propose a novel piece-wise activation function, and optimized learning rate for different datasets. Our findings first reveal that 0.01 is a preferable learning rate for the studied datasets. Third, by using an evolutionary optimization approach, we found novel piece-wise activation functions customized for TOT-Net. According to the experimental results, TOT-Net achieves 2.15%, 8.77%, and 5.7/5.52% better accuracy compared to XNOR-Net on CIFAR-10, CIFAR-100, and ImageNet top-5/top-1 datasets, respectively.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116236594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

AEx: Automated Customization of Exposed Datapath Soft-Cores AEx:自动定制暴露的数据路径软核

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00016

Alex Hirvonen, Kati Tervo, Heikki O. Kultala, P. Jääskeläinen

{"title":"AEx: Automated Customization of Exposed Datapath Soft-Cores","authors":"Alex Hirvonen, Kati Tervo, Heikki O. Kultala, P. Jääskeläinen","doi":"10.1109/DSD.2019.00016","DOIUrl":"https://doi.org/10.1109/DSD.2019.00016","url":null,"abstract":"High-level synthesis tools aim to produce hardware designs out of software descriptions with a goal to lower the bar in FPGA usage for software engineers. Despite their recent progress, however, HLS tools still require FPGA target specific pragmas and other modifications to the originally processor-targeting source code descriptions. Customized soft core based overlay architectures provide a software programmable layer on top of the FPGA fabric. The benefit of this approach is that a platform independent compiler target is presented to the programs, which lowers the porting burden, and online repurposing the same configuration is natural by just switching the executed program. The main drawback, like with any overlay architecture, are the additional implementation overheads the overlay imposes to the resource consumption and the maximum operating frequency. In this paper we show how by utilizing the efficient structure of Transport-Triggered Architectures (TTA), soft-cores can be customized automatically to benefit from the flexible FPGA fabric while still presenting a comfortable software layer to the users. The results compared to previously published non-specialized TTA soft cores indicate equal or better execution times, while the program image size is reduced by up to 49%, and overall resource utilization improved from 10% to 60%.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116446448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fault Tolerant FPGAs: Where to Spend the Effort? 容错fpga:把精力花在哪里?

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00103

M. Mousavi, S. De, H. Pourshaghaghi, H. Corporaal

{"title":"Fault Tolerant FPGAs: Where to Spend the Effort?","authors":"M. Mousavi, S. De, H. Pourshaghaghi, H. Corporaal","doi":"10.1109/DSD.2019.00103","DOIUrl":"https://doi.org/10.1109/DSD.2019.00103","url":null,"abstract":"Static Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in reallife applications, such as autonomous driving, high tech systems, and in space, where high dependability is a mandatory requirement. Since FPGA designs are stored in the Configuration Memory (CM) in SRAM-based FPGAs, they are very sensitive to Single Event Upsets (SEUs). Thus, adapting FPGA designs to make them more Fault Tolerant (FT) is extremely important. FT techniques introduce additional penalties in system parameters, like area, power consumption and performance. In order to tradeoff between the overhead introduced by FT techniques and system robustness, an accurate estimation of CM vulnerability to SEUs is needed. Many intrinsic error tolerant applications can tolerate in-exact output values to some degree. This paper shows how to exploit this property in making much cheaper FT FPGA designs with less overhead. For instance, our method can remove 51% of the area overhead for less than 0.048% output degradation, when considering a 32-bit FT adder FPGA design by applying Triple Modular Redundancy. We verify our results on various FPGA designs using a ZedBoard.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130287684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2