Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller

Abstract

In this paper, we present a parametric hardware accelerator for Takagi-Sugeno fuzzy controllers. The architecture consists of an application specific weighting function computation block, generic control output computation unit, and a programmable register file based interface. The proposed hardware design methodology is applied to a two degree of freedom robot arm controller. FPGA implementation results indicate that the hardware TS fuzzy controller supports throughputs up to 1.5 Msamples/sec, with maximum working frequencies of around 150 MHz.