Fault Tolerant FPGAs: Where to Spend the Effort?

M. Mousavi, S. De, H. Pourshaghaghi, H. Corporaal
{"title":"Fault Tolerant FPGAs: Where to Spend the Effort?","authors":"M. Mousavi, S. De, H. Pourshaghaghi, H. Corporaal","doi":"10.1109/DSD.2019.00103","DOIUrl":null,"url":null,"abstract":"Static Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in reallife applications, such as autonomous driving, high tech systems, and in space, where high dependability is a mandatory requirement. Since FPGA designs are stored in the Configuration Memory (CM) in SRAM-based FPGAs, they are very sensitive to Single Event Upsets (SEUs). Thus, adapting FPGA designs to make them more Fault Tolerant (FT) is extremely important. FT techniques introduce additional penalties in system parameters, like area, power consumption and performance. In order to tradeoff between the overhead introduced by FT techniques and system robustness, an accurate estimation of CM vulnerability to SEUs is needed. Many intrinsic error tolerant applications can tolerate in-exact output values to some degree. This paper shows how to exploit this property in making much cheaper FT FPGA designs with less overhead. For instance, our method can remove 51% of the area overhead for less than 0.048% output degradation, when considering a 32-bit FT adder FPGA design by applying Triple Modular Redundancy. We verify our results on various FPGA designs using a ZedBoard.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 22nd Euromicro Conference on Digital System Design (DSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2019.00103","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

Static Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in reallife applications, such as autonomous driving, high tech systems, and in space, where high dependability is a mandatory requirement. Since FPGA designs are stored in the Configuration Memory (CM) in SRAM-based FPGAs, they are very sensitive to Single Event Upsets (SEUs). Thus, adapting FPGA designs to make them more Fault Tolerant (FT) is extremely important. FT techniques introduce additional penalties in system parameters, like area, power consumption and performance. In order to tradeoff between the overhead introduced by FT techniques and system robustness, an accurate estimation of CM vulnerability to SEUs is needed. Many intrinsic error tolerant applications can tolerate in-exact output values to some degree. This paper shows how to exploit this property in making much cheaper FT FPGA designs with less overhead. For instance, our method can remove 51% of the area overhead for less than 0.048% output degradation, when considering a 32-bit FT adder FPGA design by applying Triple Modular Redundancy. We verify our results on various FPGA designs using a ZedBoard.
容错fpga:把精力花在哪里?
基于静态随机存取存储器(sram)的现场可编程门阵列(fpga)广泛应用于现实生活中,例如自动驾驶,高科技系统和空间,其中高可靠性是强制性要求。由于FPGA设计存储在基于sram的FPGA的配置存储器(CM)中,因此它们对单事件干扰(seu)非常敏感。因此,调整FPGA设计使其更具容错性(FT)是非常重要的。FT技术引入了额外的系统参数,如面积、功耗和性能。为了在FT技术引入的开销和系统鲁棒性之间进行权衡,需要准确估计CM对seu的脆弱性。许多固有的容错应用程序在一定程度上可以容忍不精确的输出值。本文展示了如何利用这一特性,以更低的开销制作更便宜的FT FPGA设计。例如,当考虑采用三模冗余的32位FT加法器FPGA设计时,我们的方法可以在小于0.048%的输出退化情况下去除51%的面积开销。我们使用ZedBoard在各种FPGA设计上验证了我们的结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信