{"title":"Takagi-Sugeno模糊控制器的可配置硬件加速器体系结构","authors":"O. Boncalo, A. Amaricai, Z. Lendek","doi":"10.1109/DSD.2019.00024","DOIUrl":null,"url":null,"abstract":"In this paper, we present a parametric hardware accelerator for Takagi-Sugeno fuzzy controllers. The architecture consists of an application specific weighting function computation block, generic control output computation unit, and a programmable register file based interface. The proposed hardware design methodology is applied to a two degree of freedom robot arm controller. FPGA implementation results indicate that the hardware TS fuzzy controller supports throughputs up to 1.5 Msamples/sec, with maximum working frequencies of around 150 MHz.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller\",\"authors\":\"O. Boncalo, A. Amaricai, Z. Lendek\",\"doi\":\"10.1109/DSD.2019.00024\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a parametric hardware accelerator for Takagi-Sugeno fuzzy controllers. The architecture consists of an application specific weighting function computation block, generic control output computation unit, and a programmable register file based interface. The proposed hardware design methodology is applied to a two degree of freedom robot arm controller. FPGA implementation results indicate that the hardware TS fuzzy controller supports throughputs up to 1.5 Msamples/sec, with maximum working frequencies of around 150 MHz.\",\"PeriodicalId\":217233,\"journal\":{\"name\":\"2019 22nd Euromicro Conference on Digital System Design (DSD)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 22nd Euromicro Conference on Digital System Design (DSD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DSD.2019.00024\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 22nd Euromicro Conference on Digital System Design (DSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2019.00024","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller
In this paper, we present a parametric hardware accelerator for Takagi-Sugeno fuzzy controllers. The architecture consists of an application specific weighting function computation block, generic control output computation unit, and a programmable register file based interface. The proposed hardware design methodology is applied to a two degree of freedom robot arm controller. FPGA implementation results indicate that the hardware TS fuzzy controller supports throughputs up to 1.5 Msamples/sec, with maximum working frequencies of around 150 MHz.
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