Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model

Mixed-signal applications constitute a significant trend in the semiconductor industry. Huge effort is focused on creating fast and accurate mixed-signal designs, which include both analog and digital parts. A widely used mixed-signal circuit in modern electronics is the Sigma-Delta analog-to-digital converter (ADC). Sigma-Delta modulation is mainly exploited as a method for encoding analog signals into digital signals as found in an ADC. Apart from that, it is used to convert high bit-count, low-frequency digital signals into lower bit-count, higherfrequency digital signals as part of the process to convert digital signals into analog as part of a digital-to-analog converter (DAC). In this work, a first-order Sigma-Delta ADC real number model using SystemVerilog is presented, in order to greatly improve simulation efficiency while keeping accuracy in a satisfying level. The proposed sigma-delta ADC real number model consists of a sigma-delta modulator, a digital filter and a decimator. The design and simulation of the proposed Sigma-Delta ADC model was accomplished using the Cadence Incisive Enterprise Simulator. Moreover, the proposed model is compared to a Verilog-AMS Sigma-Delta ADC, having its design implemented and simulated in Cadence Virtuoso and Spectre AMS Designer. In all test cases, the presented SystemVerilog-based real number model displays high simulation time gains, along with acceptable accuracy.