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Yttrium iron garnet thick film inclusion for enhanced microstrip patch antenna performance 提高微带贴片天线性能的钇铁石榴石厚膜包体
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069168
I. H. Hasan, M. Hamidon, I. Ismail, R. Osman, A. Ismail
{"title":"Yttrium iron garnet thick film inclusion for enhanced microstrip patch antenna performance","authors":"I. H. Hasan, M. Hamidon, I. Ismail, R. Osman, A. Ismail","doi":"10.1109/RSM.2017.8069168","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069168","url":null,"abstract":"The present investigation deals with the fabrication of silver (Ag) patch antenna with yttrium iron garnet (YIG) thick film layer inclusion as substrate overlay to enhance its performance. In this paper, YIG nanopowder was mixed with organic vehicle which consists of linseed oil, m-xylene and α-terpineol with powder ratio of 30 wt%. Then the mix was stirred at 150rpm for 3 hours at 40°C in order to obtain homogenous paste, followed by printing it onto FR4 substrate using the screen printing technique to form the YIG thick film layer before dried at 200°C. A basic square shape patch antenna by using silver paste was printed onto the YIG layer and then compared with another patch antenna which was printed without the YIG layer. The results shown that the antenna with YIG thick film layer has return loss of −19.67dB, resonant frequency 6.42GHz, bandwidth 3.13 and Q factor of 2.051, which is better compared to the antenna without the layer by 138.13%, 3.22%, 49.76% and 31.08% respectively.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131769401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Numerical study of laminar flow in pillared-micro channel 柱状微通道层流的数值研究
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069118
Wan Ammar Fikri Wan Ali, J. Yunas, A. A. Hamzah, B. Majlis
{"title":"Numerical study of laminar flow in pillared-micro channel","authors":"Wan Ammar Fikri Wan Ali, J. Yunas, A. A. Hamzah, B. Majlis","doi":"10.1109/RSM.2017.8069118","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069118","url":null,"abstract":"Numerical simulation has been conducted to analyze the fluid flow profile as well as the mixing index of laminar flow in three different shapes of pillared microchannel such as triangular prism pillar microchannel (TPP), rectangular pillar microchannel (RP), and circular pillar microchannel (CP). The ratio of the pillar to the channel's width was 1: 2. The channel was a square duct with a length of 100μm and total length of micromixer is 1900μm. The main objective of the simulation is to study the effect of pillars in microchannel towards fluid flow profiles when passing through the obstacles and on mixing performance. The analysis results show that triangular prism pillar microchannel and rectangular pillar microchannel present better mixing performance along with the increment of Reynolds number. Circular pillar microchannel does not perform accordingly to Reynolds number in the range of 10 < Re < 110. After the value of Reynolds number is above 110, circular pillar microchannel performances aligned with Reynolds number. This numerical study would give a better understanding in designing a passive micromixer model involving pillared microchannel.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131369404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and simulation of a low noise PWM based phase synchronous inverter for microgrid 微电网低噪声PWM相同步逆变器的设计与仿真
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069111
T. Rahman, S. Motakabber, M. Ibrahimy
{"title":"Design and simulation of a low noise PWM based phase synchronous inverter for microgrid","authors":"T. Rahman, S. Motakabber, M. Ibrahimy","doi":"10.1109/RSM.2017.8069111","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069111","url":null,"abstract":"A microgrid is a clear energy system consisting of demand management, storage, generation system and loads which are capable of operating in parallel or independently with the main power grid. There are some issues in the inverter circuit design which are, high frequency switching loss and noise. In addition, an electrostatic generator generates high voltage DC and low current. Any types of wave distortion or conversation losses of the inverter is a big challenged to use an electrostatic generator as an input energy source for the system. A pulse controller based switching circuit can be designed for increasing the inverter output efficiency. Herein an LCL filter has been designed to limit the THD to 3.2%. In this design, the switching frequency of the inverter is 1.65 kHz, the input supply of the inverter from an electrostatic generator of 10 kVdc, the output load of the inverter is a 100 Ω resistive load, the inverter output voltage is ±10 kVPP and the output supply frequency of the inverter is 50 Hz have been considered. The proposed inverter circuit has been simulated by MATLAB2014a. The conversion efficiency of the inverter without and with filter are observed as 66.2% and 96.8% respectively. The Phase synchronous error for each phase is approximately 5° degrees.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115574374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Numerical simulation of thick metal passivation stress, Part II: Minimizing stress using Response Surface Methodology 厚金属钝化应力的数值模拟，第二部分:使用响应面方法最小化应力
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069140
R. Sethu, David Kho, S. Kulkarni, H. U. Ha, K. Soon
{"title":"Numerical simulation of thick metal passivation stress, Part II: Minimizing stress using Response Surface Methodology","authors":"R. Sethu, David Kho, S. Kulkarni, H. U. Ha, K. Soon","doi":"10.1109/RSM.2017.8069140","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069140","url":null,"abstract":"In this two-part series of papers, the goal is to reduce thermal stress impact on thick metal passivation. In Part II (this paper), the relationship between passivation thickness and the thermal stress was established using Response Surface Methodology Design of Experiments (RSM DOe). Using RSM DOE, an optimum passivation thickness was determined and validated using the Finite Element Analysis (FEA) model used in Part I. The actual simulation results were close to the values predicted using statistical methods.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123908362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SDSoC based development of vehicle counting system using adaptive background method 基于SDSoC的自适应背景法车辆计数系统的开发
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069172
Katawut Srijongkon, Rakkrit Duangsoithong, N. Jindapetch, Masami Ikura, Surachate Chumpol
{"title":"SDSoC based development of vehicle counting system using adaptive background method","authors":"Katawut Srijongkon, Rakkrit Duangsoithong, N. Jindapetch, Masami Ikura, Surachate Chumpol","doi":"10.1109/RSM.2017.8069172","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069172","url":null,"abstract":"This paper presents a processing system of vehicle detection and counting for a camera on the city street using a heterogeneous ARM/FPGA processor and Xilinx SDSoC (Software-Defined System on Chip). An adaptive background method for reducing the impact of environment have been developed by analyzing luminance approximation changes over time and luminance approximation changes suddenly to improve background image of the object and to eliminate shadows so that the process of vehicles detecting and counting worked effectively.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"334 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123932418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Theoretical modeling and FEA simulation of a CMOS-MEMS resonator CMOS-MEMS谐振器的理论建模与有限元仿真
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069110
A. Y. Ahmed, A. Rabih, M. Khir, A. M. Basuwaqi, J. Dennis
{"title":"Theoretical modeling and FEA simulation of a CMOS-MEMS resonator","authors":"A. Y. Ahmed, A. Rabih, M. Khir, A. M. Basuwaqi, J. Dennis","doi":"10.1109/RSM.2017.8069110","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069110","url":null,"abstract":"Relative humidity sensing is crucial in many applications. However, hysteresis, lack of stability and low accuracy still exist in some of the available humidity sensors. This paper studies the effect of changing the supported beams' length and width on the resonance frequency and mass sensitivity of a CMOS-MEMS resonator proposed for relative humidity sensing applications. The resonator is designed based on 0.35 μm CMOS technology. The resonance frequency and mass sensitivity were found to be in a range of 6.195 kHz–17.852 kHz and 1.498 mHz/pg–4.301 mHz/pg, respectively, when the length of the beams was changed from 500 μm to 300 μm, while decreasing the beams' width was found to decrease the resonance frequency and subsequently the mass sensitivity. FEA simulation using 2008 CoventorWare software was used to confirm the analytical results, in which the analytical and simulation results of frequencies and mass sensitivities showed good agreement within a percentage error of 0.80 % for both of them.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123637783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The influence of shallow trench isolation angle on hot carrier effect of STI-based LDMOS transistors 浅沟槽隔离角对si基LDMOS晶体管热载子效应的影响
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069149
A. Alimin, H. H. Hizamul-Din, S. Hatta, N. Soin
{"title":"The influence of shallow trench isolation angle on hot carrier effect of STI-based LDMOS transistors","authors":"A. Alimin, H. H. Hizamul-Din, S. Hatta, N. Soin","doi":"10.1109/RSM.2017.8069149","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069149","url":null,"abstract":"Hot carrier reliability imposes challenges in the design of STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices as the device feature is miniaturized. Efforts to quantify the degradation are crucial in countering the device reliability risk. This paper investigates the effect of shallow trench isolation (STI) angle on hot carrier effect (HCI) of STI-based LDMOS devices. The effect on critical device parameters specifically the saturation drain current (Idsat), on-resistance (Ron) as well as the rate of impact ionization of the device had been studied and discussed in detail. From the result obtained, it is found that the drain current for device with 100° STI angle is reduced by 58.78% compared to device with 45° STI angle. Larger STI angle shows higher HCI degradation and the physical mechanism behind the results is analyzed from the Sentaurus 2D techplot.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"99 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114171552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Null convention logic primitive element architecture for ultralow power high performance portable digital systems 超低功耗高性能便携式数字系统的零约定逻辑基元结构
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069157
Nguyen Le Huy, P. Beckett
{"title":"Null convention logic primitive element architecture for ultralow power high performance portable digital systems","authors":"Nguyen Le Huy, P. Beckett","doi":"10.1109/RSM.2017.8069157","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069157","url":null,"abstract":"Significant challenges imposed on the design and optimization of clock-dependent systems have re-sparked interest in alternative circuit design approaches. Null Convention Logic, a quasi-delay-insensitive asynchronous design paradigm has gained significant support recently due to its intuitive circuit design and optimization approaches as well as its readiness for design automation. Just as for synchronous design, the overall performance of an NCL system will be directly affected by the performance of the individual gates. This paper presents a new NCL gate architecture based on Fully-Depleted Silicon on Insulator technology targeting ultra-low power high performance portable systems. Results indicate that NCL gates designed using the newly proposed architecture has superior performance in comparison to their conventional static and semi static CMOS counterparts and can be dynamically tuned to operate at different performance modes, allowing fine-grained tradeoffs between throughput and leakage power.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130215963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dielectric properties of ceramic materials obtained from rice husk for electronic applications 电子用稻壳陶瓷材料的介电特性
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069151
R. Osman, N. Abdullah, A. Husain, M. Hamidon, I. H. Hasan, K. Matori
{"title":"Dielectric properties of ceramic materials obtained from rice husk for electronic applications","authors":"R. Osman, N. Abdullah, A. Husain, M. Hamidon, I. H. Hasan, K. Matori","doi":"10.1109/RSM.2017.8069151","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069151","url":null,"abstract":"This paper reports on dielectric properties of ceramic material obtained from Rice Husk (RH) for electronic applications. RH is considered as agriculture waste material, contains 20–25wt% of silica (SiO2). The nanometer-sized silica powder was prepared via mechanical alloying and subsequent molding into pellet form. The compacted pellet samples were sintered at 800°C, 1000°C, 1100°C and 1200 °C respectively. Silver paste was applied on both faces of the pellet to act as electrodes. For analysis of ferroelectric polarization with respect to electric field, measurement was done using ferroelectric hysteresis loop towards the sintered pellets. The dielectric analysis was done using LCR meter. It clearly shows that dielectric constant of the samples decrease with increasing applied frequency. The capacitance is found to be decreasing with increased sintering temperatures. The result showed that WHRA does contain silica which has high dielectric constant and therefore is suitable for electronics application.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123698961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Straightforward fabrication of low schottky barrier single-walled carbon nanotube transistors by direct growth method 直接生长法制备低肖特基势垒单壁碳纳米管晶体管
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) Pub Date : 2017-08-01 DOI: 10.1109/RSM.2017.8069155
M. A. Mohamed, B. Majlis
{"title":"Straightforward fabrication of low schottky barrier single-walled carbon nanotube transistors by direct growth method","authors":"M. A. Mohamed, B. Majlis","doi":"10.1109/RSM.2017.8069155","DOIUrl":"https://doi.org/10.1109/RSM.2017.8069155","url":null,"abstract":"Single-walled carbon nanotubes field-effect transistors was fabricated by means of direct growth method. The structural of as grown CNTs directly from electrodes and the transport characteristics of the FET have been studied. SWNTs were successfully bridged the FET electrodes. For the FET device configuration in this study, the field-effectiveness can be related as Vgs:Vds = 10:−1. The enhancement of current can be attributed to the reduction of activation energy. Clear correlation between the effects of bias voltage, gate voltage and activation energy has been observed. Device operation was consistent with operation of Schottky-type FET with small Ea value of 170 meV. Ideal Schottky barrier formation for electron injection was realized in this device configuration. This study contributed to a straightforward fabrication of CNT-FET with high performance without the need of pre-deposition or post-deposition of CNTs in the FET channel.","PeriodicalId":215909,"journal":{"name":"2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122304256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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