The influence of shallow trench isolation angle on hot carrier effect of STI-based LDMOS transistors

Hot carrier reliability imposes challenges in the design of STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices as the device feature is miniaturized. Efforts to quantify the degradation are crucial in countering the device reliability risk. This paper investigates the effect of shallow trench isolation (STI) angle on hot carrier effect (HCI) of STI-based LDMOS devices. The effect on critical device parameters specifically the saturation drain current (Idsat), on-resistance (Ron) as well as the rate of impact ionization of the device had been studied and discussed in detail. From the result obtained, it is found that the drain current for device with 100° STI angle is reduced by 58.78% compared to device with 45° STI angle. Larger STI angle shows higher HCI degradation and the physical mechanism behind the results is analyzed from the Sentaurus 2D techplot.