Null convention logic primitive element architecture for ultralow power high performance portable digital systems

Abstract

Significant challenges imposed on the design and optimization of clock-dependent systems have re-sparked interest in alternative circuit design approaches. Null Convention Logic, a quasi-delay-insensitive asynchronous design paradigm has gained significant support recently due to its intuitive circuit design and optimization approaches as well as its readiness for design automation. Just as for synchronous design, the overall performance of an NCL system will be directly affected by the performance of the individual gates. This paper presents a new NCL gate architecture based on Fully-Depleted Silicon on Insulator technology targeting ultra-low power high performance portable systems. Results indicate that NCL gates designed using the newly proposed architecture has superior performance in comparison to their conventional static and semi static CMOS counterparts and can be dynamically tuned to operate at different performance modes, allowing fine-grained tradeoffs between throughput and leakage power.