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2010 International Conference on Microelectronics最新文献

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Reducing the leakage of memory blocks aggressively 积极减少内存块的泄漏
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696204
D. El-Dib, H. Shawkey, Z. Abid
{"title":"Reducing the leakage of memory blocks aggressively","authors":"D. El-Dib, H. Shawkey, Z. Abid","doi":"10.1109/ICM.2010.5696204","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696204","url":null,"abstract":"Excessive leakage of cache blocks encourages forcing the cache block into low-leakage state all the time except during read/write operations. By retaining the values of the cache cells during low leakage state, the penalty for re-activating the sleepy cache cells is also reduced. This is achieved using aggressive policies with simple control strategies using one of two methods. Either by adding a low voltage supply, operating the cache at low voltage all the time and enabling normal voltage only during a read/write operation to the cache line or by adding a ground gating NMOS transistor, which cuts the path from the supply voltage to ground all the time except during a read/write operation to the cache line. Both methods succeed to reduce leakage power during idle state by around 90% using minimum hardware control overhead, but suffer from process variation vulnerability and lower SNM.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115367531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A synchronizer design based on wagging 一种基于摆动的同步器设计
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696176
Mohammed Alshaikh, D. Kinniment, A. Yakovlev
{"title":"A synchronizer design based on wagging","authors":"Mohammed Alshaikh, D. Kinniment, A. Yakovlev","doi":"10.1109/ICM.2010.5696176","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696176","url":null,"abstract":"The reliability of a synchronizer depends on its recovery time from metastability, a time which is reduced if the delay through the synchronizer flip flops is large. The D to Q delay in a dual edge triggered D flip flop based on wagging is lower than in other designs allowing more time for metastability recovery. We also apply wagging to the synchronizer itself, reducing its delay even more when compared with conventional cascaded two flip-flops single clock cycle synchronizer, hence increasing the time available for recovery from metastability, and improving its latency. This advantage is greater in multiple cycle synchronizers.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116299541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A temperature compensated architecture for integrated, low power, frequency domain sensors 温度补偿架构集成，低功耗，频域传感器
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696105
K. Allidina, T. Saha, M. El-Gamal
{"title":"A temperature compensated architecture for integrated, low power, frequency domain sensors","authors":"K. Allidina, T. Saha, M. El-Gamal","doi":"10.1109/ICM.2010.5696105","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696105","url":null,"abstract":"This paper presents an electronic interface architecture for frequency domain capacitive and resonant sensors. The architecture provides temperature compensation without needing a high resolution temperature sensor or an integrated heater. Furthermore, it provides a fully digital output without needing a temperature independent clock to operate the time-to-digital converter. The electronic interface is analyzed theoretically for application with a MEMS-based capacitive humidity sensor, and behavioral-level simulation results are provided to verify operation. Due to the low component count and inherent temperature compensation, this architecture is well suited for compact, low power, and low cost sensing solutions in general.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129489350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A generic MP-SoC design methodology for the fast prototyping of embedded image processing 用于嵌入式图像处理快速原型的通用MP-SoC设计方法
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696084
L. Siéler, J. Derutin, L. Damez, A. Landrault
{"title":"A generic MP-SoC design methodology for the fast prototyping of embedded image processing","authors":"L. Siéler, J. Derutin, L. Damez, A. Landrault","doi":"10.1109/ICM.2010.5696084","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696084","url":null,"abstract":"This article proposes an original methodology for the fast prototyping of image processing on a generic MP-SoC (Multi-Processors System on Chip) architecture. To define a processors network adapted to a particular application is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability of an ad hoc design methodology. This paper illustrates a new methodology that enables to instantiate a generic Homogeneous Network of Communicating Processors (called HNCP) tailored for a targeted application. The HNCP is generated with a tool that avoids fastidious manual editing operations for the designer. Specific lightweight communication functions have been developed to fasten the programming of the MP-SoC network. A case study (image texture analyzes) is presented to illustrate the proposed MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129905516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of the impact of Miss Table and victim caches in parallel embedded systems 在并行嵌入式系统中Miss Table和受害者缓存的影响评估
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696100
A. Asaduzzaman, I. Mahgoub, F. Sibai
{"title":"Evaluation of the impact of Miss Table and victim caches in parallel embedded systems","authors":"A. Asaduzzaman, I. Mahgoub, F. Sibai","doi":"10.1109/ICM.2010.5696100","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696100","url":null,"abstract":"Parallel and distributed solutions are gaining increasing importance in designing embedded systems. Future parallel embedded systems are expected to have several hundred processing cores, improving the performance/power ratio. Multilevel caches in a multicore architecture require huge amount of power and may decrease processing speed due to cache's dynamic behavior. In this work, we investigate the impact of a Miss Table and victim caches at the cache level on performance and power consumption. The Miss Table holds information about the memory blocks those might cause more level-1 cache misses. Victim caches hold level-1 victim blocks. Cache locking algorithm and cache replacement scheme can directly be benefited by using the information stored in Miss Table and victim caches. We simulate a quad-core system with a two-level cache memory subsystem under MPEG4, H.264/AVC, FFT, and MI workloads. Experimental results show that the addition of the Miss Table and victim caches reduces the mean delay per task and the total power consumption by 32% and 41%, respectively.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130833147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An improved differential pull-down network logic configuration for DPA resistant circuits 一种用于抗DPA电路的改进差分下拉网络逻辑配置
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696147
J. Castro, P. Parra, A. Acosta
{"title":"An improved differential pull-down network logic configuration for DPA resistant circuits","authors":"J. Castro, P. Parra, A. Acosta","doi":"10.1109/ICM.2010.5696147","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696147","url":null,"abstract":"Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with constant power dissipation have been widely used. However, the right use of such circuits for secure applications needs not only a fully symmetric structure, but also removing any memory effect that could leak information. We propose an improved memory-less fully symmetric Xor/Xnor pull-down logic configuration, to be used with any differential technique, for immediate application in crypto-graphic secure applications.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130009020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Single Electron Artificial Neural Network (ANN) Majority Logic Gate (MLG) 单电子人工神经网络(ANN)多数逻辑门(MLG)
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696146
S. Rehan
{"title":"A Single Electron Artificial Neural Network (ANN) Majority Logic Gate (MLG)","authors":"S. Rehan","doi":"10.1109/ICM.2010.5696146","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696146","url":null,"abstract":"The Single Electron Nano-Devices (SENDs) are attractive candidates for post-CMOS VLSI era mainly due to its very low power consumption. In this paper, the Linear Threshold Gate (LTG) SEND is reviewed. An Artificial Neural Network (ANN) Majority Logic Gate (MLG) with 3 inputs (MLG3) is proposed. The MLGs with three and four inputs are implemented using LTG and SET inverter SENDs. The detailed parameters for all used devices as well as the corresponding SIMON 2.0 simulation results of these MLGs are included.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121929830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An automated SAT encoding-verification approach for efficient model checking 一种用于有效模型检查的自动SAT编码验证方法
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696177
Khaza Anuarul Hoque, O. Mohamed, Sa'ed Abed, M. Boukadoum
{"title":"An automated SAT encoding-verification approach for efficient model checking","authors":"Khaza Anuarul Hoque, O. Mohamed, Sa'ed Abed, M. Boukadoum","doi":"10.1109/ICM.2010.5696177","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696177","url":null,"abstract":"In this paper, we introduce an automated conversion-verification methodology to convert a Directed Formula (DF) into a Conjunctive Normal Form (CNF) formula that can be fed to a SAT solver. In addition, the formal verification of this conversion is conducted within the HOL theorem prover. Finally, we conduct experimental results with different-sized formulas to show the effectiveness of our methodology.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117174109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electron mobility in gate all around cylindrical silicon nanowires: A Monte Carlo study 圆柱形硅纳米线栅极周围的电子迁移率:蒙特卡罗研究
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696144
M. Ossaimee, M. El‐Sabagh, D. Selim, S. Gamal
{"title":"Electron mobility in gate all around cylindrical silicon nanowires: A Monte Carlo study","authors":"M. Ossaimee, M. El‐Sabagh, D. Selim, S. Gamal","doi":"10.1109/ICM.2010.5696144","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696144","url":null,"abstract":"Electron mobility in gated silicon nanowires is calculated using a Monte Carlo simulation that considers phonon and surface roughness scattering. Surface roughness scattering rates are calculated using Ando's model. The eigenenergies and eigenfunctions required for scattering rate calculation are determined by self-consistent solution of the Schrödinger and Poisson equations. The effects of size quantization and transverse electric field on electron mobility are presented and discussed.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117183056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Partial-Coupled Mode Space for quantum transport simulation in nanoscale double-gate MOSFETs 纳米双栅mosfet中量子输运模拟的部分耦合模式空间
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696145
M. El-Banna, Y. Sabry, W. Fikry, O. A. Omar
{"title":"Partial-Coupled Mode Space for quantum transport simulation in nanoscale double-gate MOSFETs","authors":"M. El-Banna, Y. Sabry, W. Fikry, O. A. Omar","doi":"10.1109/ICM.2010.5696145","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696145","url":null,"abstract":"A novel computationally efficient approach for simulation of quantum transport in nanoscale devices is proposed. The idea is based on partial coupling between the modes of the nanoscale device. The proposed approach, termed Partial-Coupled Mode Space (PCMS), is applied to the double-gate MOSFETs and device targets from the ITRS roadmap were simulated. A Comparison with the fully Coupled-Mode Space (CMS) was carried out. The PCMS reduces more than 65 % of the computational burden while an accuracy of better than 0.1 % and 0.01 % is maintained in the device charge and terminal current respectively.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124743801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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