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2010 International Conference on Microelectronics最新文献

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Implementation of a colorimetric algorithm for portable blood gas analysis 便携式血气分析比色算法的实现
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696175
J. Chandran, A. Stojcevski, A. Zayegh, Thinh Nguyen
{"title":"Implementation of a colorimetric algorithm for portable blood gas analysis","authors":"J. Chandran, A. Stojcevski, A. Zayegh, Thinh Nguyen","doi":"10.1109/ICM.2010.5696175","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696175","url":null,"abstract":"This paper presents the implementation results of a colorimetric algorithm for portable blood gas analysis. The need for diagnostic data to be available from the patient's living environment has given rise to the need for portable diagnostic equipment. Blood gas analysis is an important diagnostic tool which provides the medical practitioner with insights in to the health of the respiratory system and kidneys. Present day analysers are big, bulky, and expensive and run on mains supply. The paper discusses the implementation of an algorithm based on the change of colour of an indicator with respect to the change in pH. The algorithm maps the change in colour to a mathematical equation. The equation is implemented using floating point arithmetic architectures. The paper presents the implementation of the algorithm using the Altera Stratix FPGA and 0.35µm CMOS process. The design is aimed low power consumption and size. The design met the timing constraints for an operating speed of 50 MHz and consumes 2.78W of power.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123165385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the mathematical modeling of memristors 忆阻器的数学建模
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696139
A. Radwan, Mohammed Affan Zidan, K. Salama
{"title":"On the mathematical modeling of memristors","authors":"A. Radwan, Mohammed Affan Zidan, K. Salama","doi":"10.1109/ICM.2010.5696139","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696139","url":null,"abstract":"Since the fourth fundamental element (Memristor) became a reality by HP labs, and due to its huge potential, its mathematical models became a necessity. In this paper, we provide a simple mathematical model of Memristors characterized by linear dopant drift for sinusoidal input voltage, showing a high matching with the nonlinear SPICE simulations. The frequency response of the Memristor's resistance and its bounding conditions are derived. The fundamentals of the pinched i-v hysteresis, such as the critical resistances, the hysteresis power and the maximum operating current, are derived for the first time.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117141461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 101
Improved efficiency of CMOS light emitters in punch through with field oxide manipulation 利用场氧化操作提高了CMOS光源的穿孔效率
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696163
P. J. Venter, M. du Plessis, Ilse J. Nell, M. Goosen, A. Bogalecki
{"title":"Improved efficiency of CMOS light emitters in punch through with field oxide manipulation","authors":"P. J. Venter, M. du Plessis, Ilse J. Nell, M. Goosen, A. Bogalecki","doi":"10.1109/ICM.2010.5696163","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696163","url":null,"abstract":"Avalanche electroluminescence offers the opportunity for standard CMOS devices to be used as light emitters. Although inefficient, avalanche breakdown is inherently a fast process and potentially offers benefits in terms of speed when compared to emission based on forward biased junctions. Furthermore, the wide spectral characteristics of avalanche electroluminescence in the visible range also allows for some interesting applications. The main obstacle suppressing the use of these silicon light emitters in mainstream applications is inefficient radiative recombination. A number of techniques are known to improve quantum efficiency, one of which is operating the devices in punch through mode. This work focuses on improved results obtained from punch through devices, manipulation of the oxide above the radiative action and interesting results pertaining to the radiation pattern and the effects of LOCOS structures on the emission shape. This information could potentially benefit optical coupling to the light sources.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125325593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A novel SAR Fast-locking digital PLL: Behavioral modeling and simulations using VHDL-AMS 一种新型SAR快锁数字锁相环:使用VHDL-AMS进行行为建模和仿真
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696171
M. Wagdy, Anurag Nannaka
{"title":"A novel SAR Fast-locking digital PLL: Behavioral modeling and simulations using VHDL-AMS","authors":"M. Wagdy, Anurag Nannaka","doi":"10.1109/ICM.2010.5696171","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696171","url":null,"abstract":"A novel successive-approximation fast-locking digital phase-locked loop (SAR DPLL) is presented and behaviorally modeled using VHDL-AMS. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a successive-approximation algorithm similar to the one employed in SAR A/D converters (ADCs) and (2) a fine-tuning stage for phase tracking which is similar to conventional DPLLs. The coarse-tuning stage includes a frequency comparator, a successive-approximation register, a D/A converter (DAC), and control logic. Design considerations and implementation are presented in this paper. VHDL-AMS and Ansoft Simplorer are used to design and perform simulations. The fast-locking DPLL saves about 50% of the lock time as compared to its conventional DPLL counterpart.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125497186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Digitally-Controlled Variable-Gain-Amplifier based on current conveyor with opamp and inverters only 基于电流输送的仅带运放和逆变器的数控变增益放大器
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696123
F. Farag, Y. Khalaf
{"title":"Digitally-Controlled Variable-Gain-Amplifier based on current conveyor with opamp and inverters only","authors":"F. Farag, Y. Khalaf","doi":"10.1109/ICM.2010.5696123","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696123","url":null,"abstract":"This paper presents a new topology of a Digitally-Controlled current-mode-Variable-Gain-Amplifier “DCVGA”. A fully differential DCVGA is proposed, which improves the VGA performance. The proposed circuit is based on the current conveyor cell reported in [1]. The circuit is suitable for low-power low-voltage applications since it is based on CMOS inverters. The proposed DCVGA achieves linear-in-dB gain variation at 1dB resolution. The variable gain is tuned from −5 to 36 dB. The proposed circuits have been designed and simulated using 0.13 µm IBM CMOS process. The simulation results show good performance in both gain-tuning ability and frequency response. Also, the 3-dB bandwidth is about 50 kHz at maximum gain. The power dissipation is 2.1mW from 1.5V supply voltage.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126733555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ASIC Implementation of Cairo University SPARC “CUSPARC” embedded processor 开罗大学SPARC“CUSPARC”嵌入式处理器的ASIC实现
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696182
Amr A. Z. Suleiman, Alhassan F. Khedr, S. Habib
{"title":"ASIC Implementation of Cairo University SPARC “CUSPARC” embedded processor","authors":"Amr A. Z. Suleiman, Alhassan F. Khedr, S. Habib","doi":"10.1109/ICM.2010.5696182","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696182","url":null,"abstract":"Cairo University SPARC “CUSPARC” processor is an IP embedded processor core conforming to SPARC V8 ISA. CUSPARC is fully developed at Cairo University and is the first Egyptian processor. In this paper, the ASIC Implementation and Verification of the CUSPARC processor is described at 130nm technology node. CUSPARC scores a typical clock frequency of 260MHz, power dissipation of 0.11 mW/MHz and power Efficiency of 8.78 DMIPS/mW, which makes it very suitable for embedded and real-time systems.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Nanometer flip-flops design in the E-D space E-D领域的纳米人字拖设计
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696091
M. Alioto, Elio Consoli, G. Palumbo
{"title":"Nanometer flip-flops design in the E-D space","authors":"M. Alioto, Elio Consoli, G. Palumbo","doi":"10.1109/ICM.2010.5696091","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696091","url":null,"abstract":"A comprehensive design flow, easy to automate with commercial CAD tools, is presented to optimize nanometer FFs under constraints within the E-D space. By referring to practical design cases, transistor sizing is addressed rigorously. Cases of study for FFs in a 65-nm technology are reported for validation.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121224569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Semiconductor nanostructures in crystalline rare earth oxide for nanoelectronic device applications 用于纳米电子器件的晶体稀土氧化物半导体纳米结构
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696129
A. Laha, E. Bugiel, R. Ranjith, H. Osten, A. Fissel, V. Afanas’ev, M. Badylevich
{"title":"Semiconductor nanostructures in crystalline rare earth oxide for nanoelectronic device applications","authors":"A. Laha, E. Bugiel, R. Ranjith, H. Osten, A. Fissel, V. Afanas’ev, M. Badylevich","doi":"10.1109/ICM.2010.5696129","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696129","url":null,"abstract":"In this paper, we will demonstrate a novel approach to incorporate Si and/or Ge nanostructures into crystalline rare earth oxides using molecular beam epitaxy (MBE) for nanoelectronic devices application. By efficiently exploiting the growth kinetics during MBE we succeeded in creating semiconductor nanostructures exhibiting various dimensions, ranging from three dimensionally confined quantum dots (QDs) to the quantum wells, where the particles are confined in one dimension. The crystalline rare earth oxide that has been used in this study is the epitaxial gadolinium oxide (Gd2O3). The monolithic heterostructures comprised of Gd2O3-Ge/Si-Gd2O3 grown on Si substrate exhibit excellent crystalline quality with atomically sharp interface.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130068018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microelectronics implementation of directional image-based fuzzy templates for fingerprints 指纹定向图像模糊模板的微电子实现
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696150
Rosario Arjona, I. Baturone, S. Sánchez-Solano
{"title":"Microelectronics implementation of directional image-based fuzzy templates for fingerprints","authors":"Rosario Arjona, I. Baturone, S. Sánchez-Solano","doi":"10.1109/ICM.2010.5696150","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696150","url":null,"abstract":"Fingerprint orientation image, also called directional image, is a widely used method in fingerprint recognition. It helps in classification (accelerating fingerprint identification process) as well as in preprocessing or processing steps (such as fingerprint enhancement or minutiae extraction). Hence, efficient storage of directional image-based information is relevant to achieve low-cost templates not only for “match on card” but also for “authentication on card” solutions. This paper describes how to obtain a fuzzy model to describe the directional image of a fingerprint and how this model can be implemented in hardware efficiently. The CAD tools of the Xfuzzy 3 environment have been employed to accelerate the fuzzy modeling process as well as to implement the directional image-based template into both an FPGA from Xilinx and an ASIC.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134180981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigating cache parameters and locking in predictable and low power embedded systems 研究可预测和低功耗嵌入式系统中的缓存参数和锁定
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696094
A. Asaduzzaman, F. Sibai
{"title":"Investigating cache parameters and locking in predictable and low power embedded systems","authors":"A. Asaduzzaman, F. Sibai","doi":"10.1109/ICM.2010.5696094","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696094","url":null,"abstract":"We investigate the impact of cache parameters and cache locking on the predictability, power consumption, and performance of real-time embedded systems. We simulate a universally used Pentium-like CPU architecture that has two levels of cache memory hierarchy under two real-time workloads, MPEG-4 and H.264/AVC. Experimental results show that cache locking mechanism (15% CL1 locking was found to be best) added to an optimized cache memory structure is very promising for improving the predictability of embedded systems without any negative impact on the performance and total power consumption. It is also observed that H.264/AVC has a performance advantage over MPEG-4 in smaller caches.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132966815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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