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2010 International Conference on Microelectronics最新文献

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An efficient scheduling methodology for heterogeneous multi-core processor systems 异构多核处理器系统的高效调度方法
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696192
A. Elhossini, John Huissman, B. Debowski, S. Areibi, R. Dony
{"title":"An efficient scheduling methodology for heterogeneous multi-core processor systems","authors":"A. Elhossini, John Huissman, B. Debowski, S. Areibi, R. Dony","doi":"10.1109/ICM.2010.5696192","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696192","url":null,"abstract":"This paper outlines a scheduling methodology for signal processing applications onto heterogeneous multiprocessor systems. The goal is to efficiently schedule an application in the form of direct acyclic graphs (DAG), onto a heterogeneous processor environment. The solution is to use a variety of optimization techniques based on greedy methods and meta-heuristic methods to solve the problem. Results obtained indicate that the system is efficient in placing tasks to create an optimal schedule.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132600578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
SSMC: An on-chip source-synchronous multi-cycle interconnect scheme SSMC:片上源同步多周期互连方案
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696136
M. Ghoneima, Y. Ismail, M. Khellah, V. De
{"title":"SSMC: An on-chip source-synchronous multi-cycle interconnect scheme","authors":"M. Ghoneima, Y. Ismail, M. Khellah, V. De","doi":"10.1109/ICM.2010.5696136","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696136","url":null,"abstract":"In this paper, a low-power source-synchronous multi-cycle interconnect scheme SSMC is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in 3D-ICs. SSMC replaces intermediate flip-flops by a source synchronous synchronization scheme. The proposed multi-cycle bus scheme also leads to significant energy savings due to eliminating the power hungry flip-flops and efficiently designing the source synchronization overhead. Moreover, eliminating intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed and solutions are put forward to alleviate it. Circuit simulations in a 65nm process environment; indicate that energy savings up to 20% are achievable for a 6-cycle 9mm long 16-bit bus.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"2000 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131248696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Systolic-array based regularized QR-decomposition for IEEE 802.11n compliant soft-MMSE detection 基于收缩阵列的正则化qr分解用于IEEE 802.11n软mmse检测
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696169
C. Senning, Andrea Staudacher, A. Burg
{"title":"Systolic-array based regularized QR-decomposition for IEEE 802.11n compliant soft-MMSE detection","authors":"C. Senning, Andrea Staudacher, A. Burg","doi":"10.1109/ICM.2010.5696169","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696169","url":null,"abstract":"This paper considers the implementation of a soft-output MMSE detector for packet-based MIMO-OFDM transmission. The paper focuses on channel-matrix preprocessing realized with a QR decomposition which needs to be carried out under tight latency constraints. We discuss how the preprocessing algorithm should be selected to meet the specific requirements of the soft-output MMSE detector. Additionally we develop a pipelined systolic-array architecture that is particularly well suited to be combined with low-latency pipelined FFTs. We have implemented the QR decomposition method proposed for an IEEE 802.11n transceiver with 4 spatial streams. In a 0.13 µm 1P8M CMOS technology the corresponding circuit is capable to process 110 complex-valued 4×4-dimensional channel matrices for soft-output MMSE detection per second and gate equivalent and achieves a sustained throughput of 20 million decompositions per second, which is sufficient to meet the stringent latency requirements of IEEE 802.11n.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
LC-Oscillator featuring independent gate biasing implemented in 32 nm CMOS technology 采用32纳米CMOS技术实现独立门偏置的lc振荡器
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696111
D. Ponton, P. Palestri, G. Knoblinger, M. Fulde, L. Selmi
{"title":"LC-Oscillator featuring independent gate biasing implemented in 32 nm CMOS technology","authors":"D. Ponton, P. Palestri, G. Knoblinger, M. Fulde, L. Selmi","doi":"10.1109/ICM.2010.5696111","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696111","url":null,"abstract":"This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115669317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Two-phase correlated level shifting switched-capacitor techniques 两相相关移电平开关电容技术
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696109
Amr Essam, M. Dessouky, A. Zekry
{"title":"Two-phase correlated level shifting switched-capacitor techniques","authors":"Amr Essam, M. Dessouky, A. Zekry","doi":"10.1109/ICM.2010.5696109","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696109","url":null,"abstract":"In this paper, two techniques aiming to improve the performance of the switched-capacitor correlated-level-shifting technique are introduced. While boosting the equivalent opamp dc gain, this technique uses three clock phases. First, a time-shifted two-phase sampling approach is introduced with the addition of another set of sampling capacitors. However, this configuration has the disadvantages of error accumulation, increased mismatch and capacitor memory effects. In the second approach, all of these inconveniences are eliminated using a time-aligned two-phase sampling method. Simulation results show the equivalence of a conventional multiply-by-two switched-capacitor stage using a 60-dB dc gain opamp when compared with the correlated-level-shifting, the time-shifted and the time-aligned configurations, all using opamps with only 30-dB dc gain.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114884040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware realization of DC embedding video watermarking technique based on FPGA 基于FPGA的直流嵌入视频水印技术的硬件实现
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696189
Wessam S. ElAraby, A. Madian, M. Ashour, A. Wahdan
{"title":"Hardware realization of DC embedding video watermarking technique based on FPGA","authors":"Wessam S. ElAraby, A. Madian, M. Ashour, A. Wahdan","doi":"10.1109/ICM.2010.5696189","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696189","url":null,"abstract":"In this paper, a video watermark technique is proposed. The proposed technique depends on inserting invisible watermark in Low Frequency DCT domain using pseudo random number (PN) sequence generator for the video frames instead of high or mid band frequency components. This technique has been realized using Matlab and VHDL. The system has been implemented on Xilinx chip XC5VLX330T. The result of implementation shows that maximum frequency 13.61 MHZ. The experimental and implementation results has been demonstrated and discussed.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123630013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Effective screening for NBTI effect on SRAM-based memory 有效筛选NBTI对sram记忆的影响
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696167
B. Mohammad, Percy Dadabhoy
{"title":"Effective screening for NBTI effect on SRAM-based memory","authors":"B. Mohammad, Percy Dadabhoy","doi":"10.1109/ICM.2010.5696167","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696167","url":null,"abstract":"Reliability of metal-oxide-semiconductor field-effect-transistor (MOSFET) devices is a growing concern as the scaling of these devices is increased. Major contributors to the reliability issues of MOSFET devices include negative bias temperature instability (NBTI) in p-type MOSFET. NBTI phenomena causes threshold voltage shift (increasing Vt) of pMOS devices over time. This results in slow down of devices and loss of performance for logic gates. Vt shift of pMOS due to NBTI compromises SRAM stability and could cause corruption of stored data due to negative effects on Static Noise margin (SNM). It is essential to screen for NBTI effect at production time to eliminate future field failures. Current methods to screen for NBTI are expensive and inconclusive. We propose a design for test approach which enables screening for NBTI with low overhead and less test time.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121982983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Behavioral modeling of the static transfer function of ADCs using INL measurements 使用INL测量的adc静态传递函数的行为建模
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696085
R. Guindi, N. Saada
{"title":"Behavioral modeling of the static transfer function of ADCs using INL measurements","authors":"R. Guindi, N. Saada","doi":"10.1109/ICM.2010.5696085","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696085","url":null,"abstract":"In this paper, we present a modeling approach for analog-to-digital converters (ADCs) based on modeling the static transfer function using integral nonlinearity (INL) measurements. The methodology relies on applying a Fast Fourier Transform (FFT) test to the output of a real ADC circuit and extracting the significant harmonics. These are used in a behavioral functional model to approximate the INL using a polynomial function. The resulting model is independent of the ADC type or structure, and is suitable for bottom-up system verification. We compare the performance of the new model with other models based on different modeling approaches, and show a gain in simulation speed of up to 300X.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124018282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Practical design considerations on adaptive controllers for PWM DC/DC converters PWM DC/DC变换器自适应控制器的实际设计考虑
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696120
D. Della Giustina, V. Liberali
{"title":"Practical design considerations on adaptive controllers for PWM DC/DC converters","authors":"D. Della Giustina, V. Liberali","doi":"10.1109/ICM.2010.5696120","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696120","url":null,"abstract":"The paper analyzes the sensitivity to discrete and continuous parameters of an adaptive filter employed to control pulse width modulation DC/DC converters. The optimal transfer function to compensate the power cell is chosen measuring and digitalizing the inputs variables of the systems. Its synthesis is done by a digitally programmable switched capacitor circuit. The effects which can lead to a wrong estimation of the operating point and to miss the target dynamic behavior of the external feedback are discussed.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129561695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of technology shrink on audio CODEC performance 技术收缩对音频CODEC性能的影响
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696154
A. Owzar, E. Baykal, R. Teng, T. Zheng, M. Helfenstein
{"title":"Impact of technology shrink on audio CODEC performance","authors":"A. Owzar, E. Baykal, R. Teng, T. Zheng, M. Helfenstein","doi":"10.1109/ICM.2010.5696154","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696154","url":null,"abstract":"This paper presents the differences in terms of performance between 65nm and 55nm silicon for audio CODECs for mobile application. Based on representative parameters, the differences of these two technologies in terms of performance are discussed.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130016519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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