SSMC: An on-chip source-synchronous multi-cycle interconnect scheme

Abstract

In this paper, a low-power source-synchronous multi-cycle interconnect scheme SSMC is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in 3D-ICs. SSMC replaces intermediate flip-flops by a source synchronous synchronization scheme. The proposed multi-cycle bus scheme also leads to significant energy savings due to eliminating the power hungry flip-flops and efficiently designing the source synchronization overhead. Moreover, eliminating intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed and solutions are put forward to alleviate it. Circuit simulations in a 65nm process environment; indicate that energy savings up to 20% are achievable for a 6-cycle 9mm long 16-bit bus.