{"title":"Design considerations for analog blocks in mixed-signal CMOS ICs","authors":"V. Liberali, G. Trucco","doi":"10.1109/ICM.2010.5696153","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696153","url":null,"abstract":"This paper illustrates some design strategies for the design of mixed analog-digital integrated circuits in CMOS technology. In mixed-signal systems, crosstalk from switching logic gates can disturb the operation of analog circuitry. Therefore, it is necessary to take into account digital switching noise from early stages of design, by means of a suitable model. The analog designer should select the most suitable architectures with respect to crosstalk robustness. Finally, physical design must be optimized for the fabrication technology, to ensure a proper isolation between digital and analog sections.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131035434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analog digital conversion specifications for WiMAX homodyne receiver","authors":"J. Mallek, H. Mnif, M. Loulou","doi":"10.1109/ICM.2010.5696119","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696119","url":null,"abstract":"The increasing demand for wireless broadband connection emerged in Worldwide Interoperability Microwave Access (WiMAX, IEEE802.16) system which is revolutionizing the broadband wireless world by providing it with a specific standard and ensures the inter-operability among different providers. In this paper, we present the sizing of the homodyne receiver, especially the analog digital converter intended for use in the WiMAX band from 3.4 GHz to 3.6 GHz in 10 MHz channel bandwidth. For such specifications, a low-pass sigma-delta modulator for analog to digital conversion is proposed that provides variable requirements of WiMAX.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130686966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of optimized triple-mode Digital Down Converter for WCDMA, CDMA2000 and GSM of SDR","authors":"Emad S. Malki, K. Shehata, A. Madian","doi":"10.1109/ICM.2010.5696170","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696170","url":null,"abstract":"Software-Defined Radio (SDR) is a rapidly evolving Technology. SDR have been widely studied as a solution to support multiple competing and in compatible air interface standard in future wireless communications. In this paper, we present the implementation of optimized Digital Down Converter (DDC) module for triple-mode WCDMA, CDMA2000 and GSM. The designed module consists of digital mixer, CIC filter, and decimation filter and frequency converter. Theses sub-modules are software reconfigured in architecture to be compatible with WCDMA, CDMA2000 and GSM. The design is software configured with minimum hardware and maximum operating speed.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127957692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware authentication based on PUFs and SHA-3 2nd round candidates","authors":"Susana Eiroa, I. Baturone","doi":"10.1109/ICM.2010.5696149","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696149","url":null,"abstract":"Security features are getting a growing interest in microelectronics. Not only entities have to authenticate in the context of a high secure communication but also the hardware employed has to be trusted. Silicon Physical Unclonable Functions (PUFs) or Physical Random Functions, which exploits manufacturing process variations in integrated circuits, have been used to authenticate the hardware in which they are included and, based on them, several cryptographic protocols have been reported. This paper describes the hardware implementation of a symmetric-key authentication protocol in which a PUF is one of the relevant blocks. The second relevant block is a SHA-3 2nd round candidate, a Secure Hash Algorithm (in particular Keccak), which has been proposed to replace the SHA-2 functions that have been broken no long time ago. Implementation details are discussed in the case of Xilinx FPGAs.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114212824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A technique for robust division ratio switching in Multi Modulus Dividers with modulus extension","authors":"M. Eissa, M. El-Shennawy","doi":"10.1109/ICM.2010.5696212","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696212","url":null,"abstract":"This paper presents a detailed study for the logic of Multi Modulus Dividers (MMDs) with modulus extension used in low power high speed frequency synthesizers. With modulus extension, there are two division ranges (the original division range and the extended one) with a boundary between them. In this work, we will show that this architecture needs some care when used in Sigma Delta (ΣΔ) Fractional-N synthesizers, especially when the ΣΔ drives the MMD to switch back and forth this boundary. This switching should be done successfully or else the PLL will completely lose lock.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125003155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An accurate large-signal SPICE model for Resonant Tunneling Diode","authors":"Sherif F. Nafea, Ahmed A. S. Dessouki","doi":"10.1109/ICM.2010.5696201","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696201","url":null,"abstract":"Resonant Tunneling Diode (RTD) is a promising device that can be used in the design of ultra-high speed circuits. Also the Negative Differential Resistance (NDR) characteristic of RTD showed a significant reduction in logic circuits' size and complexity. This paper proposes a new accurate and less complexity large signal RTD SPICE model for analyzing circuits containing RTD. In addition, a straightforward parameters extraction routine using MATLAB program is developed. Some important applications are simulated and verified using the new model.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125284371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An analysis of SEU robustness of C-element structures implemented in bulk CMOS and SOI technologies","authors":"Z. Al Tarawneh, G. Russell, A. Yakovlev","doi":"10.1109/ICM.2010.5696138","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696138","url":null,"abstract":"Market place demands for higher performance and greater functionality per unit area have been the force driving down minimum feature sizes. However, several unintended consequences resulting from the advances in technology to address these market place demands has been an increase in the susceptibility of the circuits to SEUs and a growing uncertainty in the determination of timing parameters which is becoming detrimental to achieving timing closure. Some of the issues related to timing closure and the associated increase in power dissipation resulting from the increase in performance can be addressed through the adoption of an asynchronous design style. A logic element which is not only widely used but also peculiar to asynchronous design is the Muller C-element, which can be realised in a number of different configurations. In view of the increased susceptibility of logic elements to the effects of SEUs as device geometries are reduced this paper reports on the analysis of the robustness of various C-element configurations implemented in different technologies, to the effects of SEUs. It has been observed that of the static C-element configurations the symmetric C-element is the most robust.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122822085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. C. Moreira, C. A. Sassaki, W. Van Noije, S. Kofuji
{"title":"A 2nd derivative Gaussian UWB pulse transmitter design using a cross inductor","authors":"L. C. Moreira, C. A. Sassaki, W. Van Noije, S. Kofuji","doi":"10.1109/ICM.2010.5696116","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696116","url":null,"abstract":"This paper presents a UWB pulse transmitter design using MOSIS/IBM 0.35µm CMOS process. A 2nd order derivative Gaussian pulse is generated using a Phase Detector (PD), which consists of a D-Latch with an effective phase difference of 46ps, and at the output an extra derivative circuitry exists. It generates pulses of 100ps width. The Gaussian impulse achieves a very small pulse width of about 200ps, and amplitude of 120mVpp. The complete circuit occupies a very small area of 63.4×42.4µm2 without the PADs and inductor. The Sonnet tools were used to simulate and evaluate the performance of the novel cross inductor structure. In order to make a fair comparison, the new structure and conventional rectangular inductor were designed to get similar inductance value, and with the same segment width and spacing fixed at 10 µm. The result shows the feasibility to use the cross structure with an area of 160×140µm2, while the square planar inductor would occupy an area of 180×180µm2. Thus, the last one needs 45% more area than the cross inductor, so this cross inductor leads to an extra reduction in Silicon area, what is one of the main purposes of this work to get a small UWB transmitter. The compact shaper circuit and cross inductor has lead to the whole circuit area of only 0.0283mm2 (about 20% of other published works).","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Pipelined architecture for discrete wavelet transform implementation on FPGA","authors":"M. Bahoura, H. Ezzaidi","doi":"10.1109/ICM.2010.5696188","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696188","url":null,"abstract":"In this paper, we propose a pipelined real-time architecture for forward/inverse wavelet transforms that take into account the filter group delays. The required resources and the reconstruction error of this architecture were evaluated and compared to those of the conventional one. These architectures were implemented on FPGA using Xilinx System Generator and XUP Virtex-II Pro development board.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128017375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Rajapaksha, C. Wijenayake, A. Madanayake, L. Bruton
{"title":"Raster-scanned wave-digital filter architectures for multi-beam 2D IIR broadband beamforming","authors":"N. Rajapaksha, C. Wijenayake, A. Madanayake, L. Bruton","doi":"10.1109/ICM.2010.5696086","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696086","url":null,"abstract":"Two-dimensional (2D) beam filters find applications in highly-selective directional enhancement of spatio-temporal (ST) plane-waves (PWs). A 2D raster-scanned (RS) wave-digital filter (WDF) hardware architecture, using a uniform linear array (ULA) of sensors, based on a 2D LR-ladder prototype network is proposed for obtaining M independently-steerable broadband beams having adjustable selectivity. FPGA-based prototypes for 2,3 beams supporting upto 32 broadband sensors are as well as measured results, FPGA resource consumptions, and maximum speeds at various fixed-point precisions, are provided. On-chip verification of the M-beam 2D IIR beam WDF architecture leads to multi-beamforming in applications such as directional audio, multimedia, seismic, and ultrasonic signal processing.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133235092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}