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2010 International Conference on Microelectronics最新文献

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Parallel TLM simulation of MPSoC on SMP workstations: Influence of communication locality MPSoC在SMP工作站上的并行TLM仿真:通信局部性的影响
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696160
Isaac Maia Pessoa, A. Mello, A. Greiner, F. Pêcheux
{"title":"Parallel TLM simulation of MPSoC on SMP workstations: Influence of communication locality","authors":"Isaac Maia Pessoa, A. Mello, A. Greiner, F. Pêcheux","doi":"10.1109/ICM.2010.5696160","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696160","url":null,"abstract":"Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). SystemC TLM2.0 (Transaction Level Modeling) is now commonly used to accelerate the simulation. However, the standard SystemC simulation engine uses a centralized scheduler that is clearly a bottleneck to parallelize the simulation of architectures containing hundreds of processor cores, and involving hundreds of SC_THREADs to be scheduled. In this paper, we describe a general modeling strategy for shared memory MPSoCs and associated tools for the parallel TLM simulation of these architectures. The proposed approach is based on the Parallel Discrete Event Simulation principles, and our parallel version of the SystemC kernel (named SystemC-SMP) that can run advantageously on multiprocessor workstations. As the speedup obtained by parallel simulation depends on the communication pattern between the parallel tasks, we study the influence of various locality characteristics for the software application running on the simulated MPSoC.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133672261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Towards an automated framework for task scheduling 迈向任务调度的自动化框架
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696193
Martin Dubois, M. Boukadoum
{"title":"Towards an automated framework for task scheduling","authors":"Martin Dubois, M. Boukadoum","doi":"10.1109/ICM.2010.5696193","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696193","url":null,"abstract":"The ongoing shrinkage of semiconductor geometries allows for increasingly higher system-on-chip (SoC) densities, with more and more on-chip processors. As a result, task scheduling has become an important concern in system design and research in this area has produced substantial and diversified knowledge. This paper addresses the issue of how to effectively represent and use this knowledge in the context of design automation tools. A new methodology based on functional concept analysis is presented that structures the available task scheduling knowledge for optimal application to multiprocessor SoC design.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131911680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Design Space Exploration methodology for allocating Task Precedence graphs to multi-core system architectures 为多核系统架构分配任务优先级图的设计空间探索方法
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696133
Hassan A. Youness, Mohamed Hassan, A. Salem
{"title":"A Design Space Exploration methodology for allocating Task Precedence graphs to multi-core system architectures","authors":"Hassan A. Youness, Mohamed Hassan, A. Salem","doi":"10.1109/ICM.2010.5696133","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696133","url":null,"abstract":"In this paper, we propose a Design Space Exploration (DSE) methodology to produce multi-core system architectures with optimal scheduling, number of cores, number of buses and hardware-software partitioning from Task Precedence Graphs (TPGs). The viability and potential of the proposed methodology is demonstrated by extensive experimental results to conclude that it is an efficient scheme to obtain the optimality with hard and large task graph problems.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115050032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ENOB calculation for ADCs with input-correlated quantization error using a sine-wave test 使用正弦波测试计算输入相关量化误差的adc的ENOB
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696205
S. Weaver, B. Hershberg, U. Moon
{"title":"ENOB calculation for ADCs with input-correlated quantization error using a sine-wave test","authors":"S. Weaver, B. Hershberg, U. Moon","doi":"10.1109/ICM.2010.5696205","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696205","url":null,"abstract":"The equation for calculating ENOB from SNDR of a sine-wave test is only accurate when noise is uncorrelated to the input. In this paper, the equation for calculating ENOB from SNDR is derived for an ideal and a uniform stochastic ADC. The result of these derivations shows that calculating ENOB from SNDR using the conventional equation causes a better-than-actual result in the case a uniform stochastic ADC.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115709459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A multi-megarad, radiation hardened by design 512 kbit SRAM in CMOS technology 采用CMOS技术设计了512 kbit SRAM，实现了多兆位抗辐射
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696165
C. Calligaro, V. Liberali, A. Stabile, M. Bagatin, S. Gerardin, A. Paccagnella
{"title":"A multi-megarad, radiation hardened by design 512 kbit SRAM in CMOS technology","authors":"C. Calligaro, V. Liberali, A. Stabile, M. Bagatin, S. Gerardin, A. Paccagnella","doi":"10.1109/ICM.2010.5696165","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696165","url":null,"abstract":"This paper describes a SRAM designed for space and nuclear physics applications. The device has been designed in a commercial 180 nm CMOS technology using RHBD techniques. Measurement on prototype samples under radiation demonstrate immunity to total dose and latch-up, and an adequate level of hardness with respect to single event effects.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115145826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Decimal Floating Point for future processors 未来处理器的十进制浮点数
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696183
H. Fahmy, Tarek ElDeeb, M. Hassan, Yasmin Farouk, R. R. Eissa
{"title":"Decimal Floating Point for future processors","authors":"H. Fahmy, Tarek ElDeeb, M. Hassan, Yasmin Farouk, R. R. Eissa","doi":"10.1109/ICM.2010.5696183","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696183","url":null,"abstract":"Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused-multiply-add compliant with the IEEE 754–2008 standard. This paper presents the results of using our units as part of a vector co-processor and the anticipated gains once the units are moved on chip with the main processor.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121407605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Esd Protection circuits with low triggering vlotage, low leakage current and fast turn-on Esd保护电路，触发电压低，漏电流小，开通快
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696214
Yong-Seo Koo, Kwang-Yeob Lee, Hyun-Duck Lee, Tae-Ryoung Park, Jae-Chang Kwak, Yil Suk Yang
{"title":"Esd Protection circuits with low triggering vlotage, low leakage current and fast turn-on","authors":"Yong-Seo Koo, Kwang-Yeob Lee, Hyun-Duck Lee, Tae-Ryoung Park, Jae-Chang Kwak, Yil Suk Yang","doi":"10.1109/ICM.2010.5696214","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696214","url":null,"abstract":"ESD Protection circuits with low triggering voltage, low leakage current and fast turn-on using trigger techniques are presented in this paper. The proposed ESD protection devices are designed in 0.13um CMOS Technology. The results show that the proposed substrate Triggered NMOS using bipolar transistor has a lower trigger voltage of 5.98V and a faster turn-on time of 37ns. And the results show that the proposed gate-substrate triggered NMOS have lower trigger voltage of 5.35V and lower leakage current of 80pA.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130560181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CMOS ring oscillators with enhanced frequency operation 具有增强频率操作的CMOS环形振荡器
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696113
A. El mourabit, G. Lu, Ming Zhang, P. Pittet, Youness Birjali, Fouad Lahjoumri
{"title":"CMOS ring oscillators with enhanced frequency operation","authors":"A. El mourabit, G. Lu, Ming Zhang, P. Pittet, Youness Birjali, Fouad Lahjoumri","doi":"10.1109/ICM.2010.5696113","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696113","url":null,"abstract":"This paper presents a new technique to improve frequency performance of CMOS ring oscillator. It is based on the adding of a CR differentiators-based MOS transistor to boost switching speed of the oscillator delay cell. The method can be used for simple and differential oscillator and offers a simple way to implement frequency tuning without introduction of any additional phase noise. Using 0.35 µm CMOS technology, simulation results show that applying the technique to the simple ring oscillator allows a frequency oscillation improvement of 78 %. Also, simulations show that frequency improvement can reach 250 % if the technique is associated to a positive feedback.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130855498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement of continuous-time ΣΔ modulators: Implications of using spectrum analyzer 连续时间ΣΔ调制器的测量:使用频谱分析仪的意义
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696216
A. Ashry, Ahmed K. El-Shennawy, M. Elbadry, A. Elsayed, H. Aboushady
{"title":"Measurement of continuous-time ΣΔ modulators: Implications of using spectrum analyzer","authors":"A. Ashry, Ahmed K. El-Shennawy, M. Elbadry, A. Elsayed, H. Aboushady","doi":"10.1109/ICM.2010.5696216","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696216","url":null,"abstract":"In this paper, The difference between getting the output spectrum directly using spectrum analyzer and obtaining the spectrum digitally in measuring clock jitter effect on continuous-time ΣΔ modulator is analyzed. It is shown that clock jitter can be seen as input-referred or output-referred, depending on the nature of the measurement tool. Quantization noise and jitter noise are analyzed and compared graphically using a simple approach. The presented analysis is verified with system-level simulation of a 4th order bandpass continuous-time ΣΔ modulator.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130665611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The interlaced carry-arrest adder 交错进位加法器
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696088
A. Fam
{"title":"The interlaced carry-arrest adder","authors":"A. Fam","doi":"10.1109/ICM.2010.5696088","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696088","url":null,"abstract":"The interlaced carry-arrest adder (ICA) is introduced as a new, fast multioperand adder to compute the sum of four or more numbers. To avoid the need to propagate the carry all the way to the most significant bits, periodic gaps of zeros are created in each of the summands by moving certain pattern of their bits into auxiliary arrays. The pattern of the moved bits is staggered, such that the auxiliary arrays are filled without overlaps and with a periodic pattern of gaps left unfilled such that the resulting auxiliary numbers also have the same staggered zero patterns as the summands. These gaps convert a sum of numbers with arbitrarily large number of bits to independent parallel additions of short pairs of numbers. This is so since any carry bits resulting from the addition of pairs of short numbers are trapped in the gaps. This allows for fast parallel addition that is truly independent of the number of bits of the summands, and depend only on the number of bits in the short numbers added in parallel, and logarithmically on the number of numbers to be added.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133474977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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