{"title":"离散小波变换在FPGA上的流水线结构实现","authors":"M. Bahoura, H. Ezzaidi","doi":"10.1109/ICM.2010.5696188","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a pipelined real-time architecture for forward/inverse wavelet transforms that take into account the filter group delays. The required resources and the reconstruction error of this architecture were evaluated and compared to those of the conventional one. These architectures were implemented on FPGA using Xilinx System Generator and XUP Virtex-II Pro development board.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Pipelined architecture for discrete wavelet transform implementation on FPGA\",\"authors\":\"M. Bahoura, H. Ezzaidi\",\"doi\":\"10.1109/ICM.2010.5696188\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a pipelined real-time architecture for forward/inverse wavelet transforms that take into account the filter group delays. The required resources and the reconstruction error of this architecture were evaluated and compared to those of the conventional one. These architectures were implemented on FPGA using Xilinx System Generator and XUP Virtex-II Pro development board.\",\"PeriodicalId\":215859,\"journal\":{\"name\":\"2010 International Conference on Microelectronics\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Microelectronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2010.5696188\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2010.5696188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
在本文中，我们提出了一种考虑滤波器组延迟的正/逆小波变换的流水线实时体系结构。评估了该体系结构所需资源和重构误差，并与传统体系结构进行了比较。这些架构在FPGA上使用Xilinx System Generator和XUP Virtex-II Pro开发板实现。
Pipelined architecture for discrete wavelet transform implementation on FPGA
In this paper, we propose a pipelined real-time architecture for forward/inverse wavelet transforms that take into account the filter group delays. The required resources and the reconstruction error of this architecture were evaluated and compared to those of the conventional one. These architectures were implemented on FPGA using Xilinx System Generator and XUP Virtex-II Pro development board.
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