An analysis of SEU robustness of C-element structures implemented in bulk CMOS and SOI technologies

Abstract

Market place demands for higher performance and greater functionality per unit area have been the force driving down minimum feature sizes. However, several unintended consequences resulting from the advances in technology to address these market place demands has been an increase in the susceptibility of the circuits to SEUs and a growing uncertainty in the determination of timing parameters which is becoming detrimental to achieving timing closure. Some of the issues related to timing closure and the associated increase in power dissipation resulting from the increase in performance can be addressed through the adoption of an asynchronous design style. A logic element which is not only widely used but also peculiar to asynchronous design is the Muller C-element, which can be realised in a number of different configurations. In view of the increased susceptibility of logic elements to the effects of SEUs as device geometries are reduced this paper reports on the analysis of the robustness of various C-element configurations implemented in different technologies, to the effects of SEUs. It has been observed that of the static C-element configurations the symmetric C-element is the most robust.