D. Ponton, P. Palestri, G. Knoblinger, M. Fulde, L. Selmi
{"title":"采用32纳米CMOS技术实现独立门偏置的lc振荡器","authors":"D. Ponton, P. Palestri, G. Knoblinger, M. Fulde, L. Selmi","doi":"10.1109/ICM.2010.5696111","DOIUrl":null,"url":null,"abstract":"This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"LC-Oscillator featuring independent gate biasing implemented in 32 nm CMOS technology\",\"authors\":\"D. Ponton, P. Palestri, G. Knoblinger, M. Fulde, L. Selmi\",\"doi\":\"10.1109/ICM.2010.5696111\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators.\",\"PeriodicalId\":215859,\"journal\":{\"name\":\"2010 International Conference on Microelectronics\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Microelectronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2010.5696111\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2010.5696111","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators.