Investigating cache parameters and locking in predictable and low power embedded systems

Abstract

We investigate the impact of cache parameters and cache locking on the predictability, power consumption, and performance of real-time embedded systems. We simulate a universally used Pentium-like CPU architecture that has two levels of cache memory hierarchy under two real-time workloads, MPEG-4 and H.264/AVC. Experimental results show that cache locking mechanism (15% CL1 locking was found to be best) added to an optimized cache memory structure is very promising for improving the predictability of embedded systems without any negative impact on the performance and total power consumption. It is also observed that H.264/AVC has a performance advantage over MPEG-4 in smaller caches.