Reducing the leakage of memory blocks aggressively

Abstract

Excessive leakage of cache blocks encourages forcing the cache block into low-leakage state all the time except during read/write operations. By retaining the values of the cache cells during low leakage state, the penalty for re-activating the sleepy cache cells is also reduced. This is achieved using aggressive policies with simple control strategies using one of two methods. Either by adding a low voltage supply, operating the cache at low voltage all the time and enabling normal voltage only during a read/write operation to the cache line or by adding a ground gating NMOS transistor, which cuts the path from the supply voltage to ground all the time except during a read/write operation to the cache line. Both methods succeed to reduce leakage power during idle state by around 90% using minimum hardware control overhead, but suffer from process variation vulnerability and lower SNM.