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An ultra-low power voltage regulator for wireless sensor nodes 一种用于无线传感器节点的超低功耗电压调节器
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696121
Stefan Gruber, Hannes Reinisch, Hartwig Unterassinger, Martin Wiessflecker, G. Hofer, W. Pribyl, G. Holweg
{"title":"An ultra-low power voltage regulator for wireless sensor nodes","authors":"Stefan Gruber, Hannes Reinisch, Hartwig Unterassinger, Martin Wiessflecker, G. Hofer, W. Pribyl, G. Holweg","doi":"10.1109/ICM.2010.5696121","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696121","url":null,"abstract":"This paper presents an ultra-low power voltage regulator used for low power wireless sensor nodes. As the input conditions for these types of regulators can be quite different in terms of voltage range and transient speed, the introduced architecture is designed to be almost insensitive to these variations. Even if the pass device is formed by an NMOS transistor, low-dropout operation is possible by the utilization of a charge pump. The focus is on reducing the energy consumption of the regulator while keeping the robustness high. The regulator does not need an external compensation device. The circuit, implemented in a 0.13 µm CMOS process, generates the supply voltage for an ultra-low power temperature sensor and an ADC. Implementation and experimental results are discussed.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134389845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of on-chip link performance under area, power and variability constraints 在面积、功率和可变性约束下的片上链路性能优化
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696196
Faiz-ul-Hassan, F. Rodríguez-Salazar, W. Vanderbauwhede
{"title":"Optimization of on-chip link performance under area, power and variability constraints","authors":"Faiz-ul-Hassan, F. Rodríguez-Salazar, W. Vanderbauwhede","doi":"10.1109/ICM.2010.5696196","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696196","url":null,"abstract":"A large number of repeaters are used in the global interconnects of any System-on-Chip (SoC) design for improving the delay characteristics, and these repeaters consume a significant portion of the chip area and power. In this work we emphasize that due to increasing trend of the variability, power and area optimal repeater insertion methodologies should also consider performance variability. Analytical models for area, power, performance and probability of link failure have been presented in terms of the size of the repeaters and inter-repeater segment length. It has been found that beyond a certain reduction in the size of the repeaters, the delay variability may exceed acceptable limits while still satisfying other constraints. For instance, with only 4% of performance loss due to the use of smaller repeaters, almost 30% of power and 40% of area savings can be achieved; however performance certainty is reduced by 24%. Therefore, while optimizing area, power and performance of on-chip communication links, delay (and power) variability should also be included in the figure of merit.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new datapath-oriented tree-based FPGA architecture 一种新的面向数据路径的树型FPGA架构
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696172
Umer Farooq, Z. Marrakchi, H. Mehrez
{"title":"A new datapath-oriented tree-based FPGA architecture","authors":"Umer Farooq, Z. Marrakchi, H. Mehrez","doi":"10.1109/ICM.2010.5696172","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696172","url":null,"abstract":"During past few years FPGAs have seen a rapid growth in their logic capacity which has led to the increasing use of FPGAs for the implementation of arithmetic-intensive applications. Arithmetic-intensive applications often contain large portion of datapath circuits. Datapath circuits usually contain hard-blocks (e.g. multipliers, adders, memories etc) that are connected together by regularly structured signals called buses. Conventional FPGAs do not use the regularity of datapath circuits. So it is possible to modify the conventional FPGA architectures to exploit the regularity of datapath circuits and achieve significant area savings. This paper describes a new tree-based FPGA architecture that uses bus-based connections and exploits the regularity of datapath circuits to achieve area savings. Experiments show that the proposed architecture is 24%, 21% more area efficient than conventional mesh-based and tree-based architectures respectively.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116191829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scanned-array audio beamforming using 2nd- and 3rd-order 2D IIR beam filters on FPGA 在FPGA上使用二阶和三阶二维IIR波束滤波器的扫描阵列音频波束形成
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696186
N. Ganganath, G. Attanayake, T. Bandara, P. Ilangakoon, R. Rodrigo, A. Madanayake, L. Bruton
{"title":"Scanned-array audio beamforming using 2nd- and 3rd-order 2D IIR beam filters on FPGA","authors":"N. Ganganath, G. Attanayake, T. Bandara, P. Ilangakoon, R. Rodrigo, A. Madanayake, L. Bruton","doi":"10.1109/ICM.2010.5696186","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696186","url":null,"abstract":"Real-time scanned-array direct-form-I hardware implementations of two-dimensional (2D) infinite impulse response (IIR) frequency-planar beam plane-wave (PW) filters have potentially wide applications in the directional enhancement of spatio-temporal broadband PWs based on their directions of arrival (DOAs). The proposed prototypes consist of a microphone sensor array, low-noise-amplifiers (LNAs), multiplexers (MUXs), a programmable gain amplifier (PGA), an analog to digital converter (ADC), a digital to analog converter (DAC), and a field programmable gate array (FPGA) circuit based 2D IIR spatio-temporal beam filter implemented on a single Xilinx Virtex2P xc2vp30-7ff896 FPGA chip. Starting from published 1st-order designs, novel FPGA architectures for highly-selective 2nd- and 3rd-order beam PW filters are proposed, simulated, implemented on FPGA, and verified on-chip.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125018872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New ± 0.75 V low voltage low power CMOS current conveyor 新型±0.75 V低压低功率CMOS电流输送装置
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696122
Ahmed H. M. Abolila, H. Hamed, E. Hasaneen
{"title":"New ± 0.75 V low voltage low power CMOS current conveyor","authors":"Ahmed H. M. Abolila, H. Hamed, E. Hasaneen","doi":"10.1109/ICM.2010.5696122","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696122","url":null,"abstract":"In this paper a new low voltage low power class AB CMOS second generation current conveyor (CCII) based on Rail-to-Rail folded cascode Op-Amp is presented, with a great performance. The proposed CCII provides very low input impedance at X-port, very high input impedance at Y-port, accurate voltage and current tracking with low offset, and wide bandwidth. As an application, a four quadrant analog multiplier has been built based on the proposed CCII. The proposed CCII performance has been investigated by Pspice simulation program using TSMC 0.18 µm CMOS technology. The presented CCII is supplied at ± 0.75 V.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127243530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Analytical modeling and simulation studies of high voltage super-junction drift layer for power MOSFET 功率MOSFET高压超结漂移层的解析建模与仿真研究
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696198
P. Kondekar
{"title":"Analytical modeling and simulation studies of high voltage super-junction drift layer for power MOSFET","authors":"P. Kondekar","doi":"10.1109/ICM.2010.5696198","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696198","url":null,"abstract":"In the conventional VDMOS high voltage super-junction (SJ) power transistor, to achieve high breakdown voltage (BV), you have to use lower doping and higher thickness of the drift layer which prohibitively increases it on resistance making it unsuitable for use. Super-junction power MOSFET (CoolMOS™) claim to resolve this limitation and high voltage device up 1000V are using super junction drift layer with relatively low on resistance. In this paper an effort is made to explain in detail with the help of analytical treatment and simulation results to understand the physical mechanisms involved in improving the on resistance with high BV. An analytical modeling method is also proposed to get the design guide line for device dimensions and optimum doping levels for minimum on resistance based on Super-junction Theory.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126301151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Large area CVD monolayer graphene for nanoelectronics: Device performance and analysis 纳米电子学用大面积CVD单层石墨烯:器件性能与分析
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696125
O. Nayfeh, M. Dubey
{"title":"Large area CVD monolayer graphene for nanoelectronics: Device performance and analysis","authors":"O. Nayfeh, M. Dubey","doi":"10.1109/ICM.2010.5696125","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696125","url":null,"abstract":"Graphene transistors using large area CVD monolayer graphene are constructed and examined. Back-gated devices with exposed graphene channels are characterized to shed light on some of the apparent doping and transport effects that could impact the device performance. Electrical measurements under vacuum and soft-anneal conditions are used to modulate the effective doping density and carrier mobility for both electrons and holes. A good agreement between measurements and a simple drift-diffusion model is obtained when modeling this CVD graphene with a net p-type doping and asymmetric electron/hole mobility. An extracted mean-free path for scattering suggests the presence of large levels of Coulomb and short-range scattering which could be limiting the mobility in this doped material. The results are of importance for understanding the potential of large-area CVD graphene for use in future radiofrequency devices.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128146953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Blood glucose sensor implant using NIR spectroscopy: Preliminary design study 使用近红外光谱植入血糖传感器:初步设计研究
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696108
A. Trabelsi, M. Boukadoum, C. Fayomi, E. Aboulhamid
{"title":"Blood glucose sensor implant using NIR spectroscopy: Preliminary design study","authors":"A. Trabelsi, M. Boukadoum, C. Fayomi, E. Aboulhamid","doi":"10.1109/ICM.2010.5696108","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696108","url":null,"abstract":"We previously proposed in [1] a novel standalone fluorescence measurement device that can identify fluorophore substances in a light conducting environment. In this paper, we adapt this work to the particular problem of predicting blood glucose levels based on near-infrared (NIR) absorption spectroscopy. We have focused this investigation on the combination (5000–4000 cm−1) and first-overtone (6500–5500 cm−1) spectral bands known to be dominated by glucose absorption information. An array of electrically pumped vertical-cavity surface-emitting lasers (VCSELs) is used to cover the two selected spectral bands; with each laser diode emitting light at a specific wavelength. A Quantum well infrared (QWI) photodetector operating in the 1.2–2.5 µm range is used for optical power detection. Then, an artificial neural network (ANN) based model is used to determine the glucose concentrations from the obtained blood absorption spectra.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A continuous analysis of the oscillation amplitude in MOS LC-VCOs MOS lc - vco振荡幅度的连续分析
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696114
B. Fahs, P. Gamand, C. Berland
{"title":"A continuous analysis of the oscillation amplitude in MOS LC-VCOs","authors":"B. Fahs, P. Gamand, C. Berland","doi":"10.1109/ICM.2010.5696114","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696114","url":null,"abstract":"In this paper, a closed-form expression for oscillation amplitude in source-tailed MOS LC-VCOs versus the oscillator bias current and LC-tank resistive losses is proposed. The developed analysis is based on the utilization of analog saturation functions to provide a continuous equation among the oscillator's current-limited and voltage-limited regimes, which takes also into account the oscillation start-up condition. Quantitative predictions from the derived equation are in good agreement with Spectre simulations results from a 0.25-µm technology LC-VCO circuit. This expression can be used in an equation-based algorithm serving to control the amplitude and to optimize the phase noise versus frequency setting in switched-resonator based LC-VCOs.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132503518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An energy recovery approach for a charge redistribution successive approximation ADC 电荷再分布逐次逼近 ADC 的能量回收方法
2010 International Conference on Microelectronics Pub Date : 2010-12-01 DOI: 10.1109/ICM.2010.5696093
Howard Tang, S. Liter
{"title":"An energy recovery approach for a charge redistribution successive approximation ADC","authors":"Howard Tang, S. Liter","doi":"10.1109/ICM.2010.5696093","DOIUrl":"https://doi.org/10.1109/ICM.2010.5696093","url":null,"abstract":"This paper presents a new method to recover energy in an Analog-to-Digital Converter (ADC) based on the principle of adiabatic charging. The ADC comprises an Adiabatic Charging Charge Redistribution (ACCR) DAC, a dynamic comparator, and a Successive-Approximation-Register (SAR) counter. Charges in the ACCR DAC can be recovered through a resonant power supply and adiabatic switch. These charges can then be stored for reuse, thus, provide a design approach for highly energy efficient ADC. The adiabatic switch is designed with two operation modes - Fast Switching Mode and Adiabatic Mode. Therefore, the ACCR DAC can operate at its fastest possible sampling rate during Fast Switching Mode and achieve highest energy efficiency during Adiabatic Mode. A 10-bit ACCR DAC using 0.18µm CMOS technology is simulated with SPICE. Simulation results show that the ACCR DAC achieves an energy efficiency of 30.42 fJ/conversion-step during Adiabatic Mode at a sampling rate of 100kS/s with 2V supply voltage. This is translated into an improvement of 69% as compared to the conventional switching method.","PeriodicalId":215859,"journal":{"name":"2010 International Conference on Microelectronics","volume":"30 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126860917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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