2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)最新文献_第10页

Methodology To execute SPARC binary of Silterra memory compiler 0.18um process technology on x86 Architecture 在x86架构上执行0.18um进程技术的Silterra内存编译器的SPARC二进制文件

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417189

R. Aziz, R. Baharim, M. H. M. Nasir, R. A. Wahab, N. Othman, N. Razali, S. Saleh

引用次数: 0

Design of low power, low jitter DLL tested at all five corners to avoid false locking 设计低功耗、低抖动的DLL，在所有五个角进行测试，避免误锁

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417201

H. S. Raghav, S. Maheshwari, M. Srinivasarao, B. P. Singh

{"title":"Design of low power, low jitter DLL tested at all five corners to avoid false locking","authors":"H. S. Raghav, S. Maheshwari, M. Srinivasarao, B. P. Singh","doi":"10.1109/SMELEC.2012.6417201","DOIUrl":"https://doi.org/10.1109/SMELEC.2012.6417201","url":null,"abstract":"A modified Phase Selection Circuit, a modified Phase Frequency Detector and a modified Voltage Controlled Delay Line is proposed to improve the Delay Locked Loops (DLL) locking time, lock range and the jitter performance. Also the DLL presented in this paper has a wide-range frequency operation. A modified Phase Selection circuit is designed in order to operate DLL over wide frequency range and completely solve the false locking problem. Also a Modified Phase Frequency detector circuit has been designed to reduce the phase error as well as dead-zone situation. The proposed DLL design is simulated in Cadence Spectre using TSMC 180nm CMOS Technology and 1.8V power supply voltage operate correctly when the input clock frequency is changed from 84 to 800MHz and generate ten-phase clocks within just one clock cycle. The simulation is performed for all five process corners. The DLL consumes maximum power of 6.85mW at 800MHz working at FF corner, whereas, the maximum peak-to-peak jitter is 4ps at 84MHz working at FS corner. Both maximum power and jitter is measured at temperature and voltage of -40°C and 1.98V.","PeriodicalId":210558,"journal":{"name":"2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128868179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Organic field-effect transistors for nonvolatile memory devices using charge-acceptor layers 使用电荷受体层的非易失性存储器器件用有机场效应晶体管

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417252

K. A. Mohamad, A. Alias, Ismail Saad, B. Gosh, Katsuhiro Uesugi, Hisashi Fukuda

引用次数: 0

Thermal effects in InAs/GaAs quantum dot vertical cavity surface emitting lasers InAs/GaAs量子点垂直腔面发射激光器的热效应

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417075

Y. S. Fatt

{"title":"Thermal effects in InAs/GaAs quantum dot vertical cavity surface emitting lasers","authors":"Y. S. Fatt","doi":"10.1109/SMELEC.2012.6417075","DOIUrl":"https://doi.org/10.1109/SMELEC.2012.6417075","url":null,"abstract":"Summary form only given. The performance of 1.3-μm InAs/GaAs quantum dot (QD) vertical cavity surface emitting lasers (VCSELs) is adversely affected by self-heating effect. In this talk, a self-consistent model comprising rate equations and thermal conduction equation will be presented to analyze the influence of self-heating on the carrier dynamics and output power of QD VCSELs. The simulation results indicate that the low output power is attributed to hole thermalization and escape due to the thin wetting layer. The hole confinement can be improved by increasing the number of QD layers and surface density, as well as adopting p-type modulation doping. The fabricated p-doped QD VCSELs exhibit high temperature stability in the threshold current. The highest output power of 0.435 mW and lowest threshold current of 1.2 mA under single-mode operation were achieved, with side mode suppression ratio (SMSR) of 34 dB at room temperature (RT). However, the output power is limited by the small-sized oxide apertures. To achieve both high output power and enhancement of the fundamental mode emission, a dielectric-free (DF) approach with surface-relief (SR) technique is applied in our device fabrication. Compared with the conventional dielectric-dependent (DD) method, the DF approach potentially reduces the fabrication cost and complexity. Moreover, with the same oxide aperture area, the differential resistance is reduced by 36.47% and output power is improved by 78.32% under continuous-wave (CW) operation. The output power increases up to 3.42 mW under pulsed operation with oxide aperture diameter of ~15 μm. The surface-relief technique effectively enhances the fundamental mode emission of the QD VCSEL.","PeriodicalId":210558,"journal":{"name":"2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Calibration parameters in TCAD for predictive MOSFET device simulations TCAD中用于预测MOSFET器件仿真的校准参数

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417137

M. A. Ismail, M. H. A. Bakar, I. M. Nasir

引用次数: 0

An improved P+/N diode leakage current in BiCMOS technologies with fluorine co-implant 氟共植入提高了BiCMOS技术中P+/N二极管漏电流

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417237

S. Z. M. Saad, T. C. Lik, M. A. Othman, P. Holger, S. H. Herman

引用次数: 2

Modulus and thermal properties of free standing PMMA/TiO2 nanocomposite films 独立PMMA/TiO2纳米复合膜的模量和热性能

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417119

N. N. Hafizah, L. N. Ismail, M. Rusop

引用次数: 0

Design and simulation of high magnetic gradient device for effective bioparticles trapping 高效捕获生物微粒的高磁梯度装置的设计与仿真

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417122

U. Abidin, B. Majlis, J. Yunas

{"title":"Design and simulation of high magnetic gradient device for effective bioparticles trapping","authors":"U. Abidin, B. Majlis, J. Yunas","doi":"10.1109/SMELEC.2012.6417122","DOIUrl":"https://doi.org/10.1109/SMELEC.2012.6417122","url":null,"abstract":"In this work, a design and simulation of high magnetic gradient device for effective bioparticles trapping is reported. The planar square-shaped microcoil and a V-shaped nickel iron (NiFe) alloy core is designed to guide and confine the magnetic flux lines through its small tip area and thus enhance the magnetic flux density and its gradient. The effects of core structure and coil parameters are analyzed using Finite element analysis (FEA) of two dimensional axial symmetry modeling. The simulation results revealed that the V-shaped magnetic core has significantly increased the magnetic flux density, its gradient and the magnetic force affecting on the beads sample. The highest magnetic flux density value, Bnorm is 66 mT is achieved for microcoil turns of N = 20, thickness of h = 5 μm, width and spacing of w = s = 50 μm and on tip surface area of 1 μm2. Furthermore, a maximum magnetic force value of Fm = 1700 pN which is much higher than the drag force experienced by the magnetic beads in the microchannel has also been observed. Therefore, a promising effective trapping of the magnetic beads in the microfluidic channel is enable with this high magnetic gradient device design.","PeriodicalId":210558,"journal":{"name":"2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120918903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fabrication and characterization of Pb1−xYbxTe based alloy thin film thermoelectric generators using thermal evaporation method 采用热蒸发法制备Pb1−xYbxTe基合金薄膜热电发生器并进行表征

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417245

A. Kadhim, A. Abbas, H. A. Hassan

引用次数: 0

Study of ZnO micro-gap on SiO2/Si substrate by conventional lithography method for pH measurement 用常规光刻法测量pH值在SiO2/Si衬底上ZnO微间隙的研究

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI: 10.1109/SMELEC.2012.6417121

K. L. Foo, U. Hashim, H. Prasad, M. Kashif

引用次数: 6