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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)最新文献

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Sub-sampling sigma-delta modulator for baseband processing 用于基带处理的次采样σ - δ调制器
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012796
Srinivasaraman Chandrasekaran, W. Black
{"title":"Sub-sampling sigma-delta modulator for baseband processing","authors":"Srinivasaraman Chandrasekaran, W. Black","doi":"10.1109/CICC.2002.1012796","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012796","url":null,"abstract":"A sigma-delta (SD) modulator has been developed for baseband processing in a direct conversion receiver (DCR). A second-order SD modulator with a subsampling mixer, inside the feedback loop, down-converts the incoming RF signals directly to baseband, digitizes them and attenuates noise as well as interferers. A prototype was fabricated in a TSMC 0.25 /spl mu/m process for use in a CDMA2000 transceiver. SNR greater than 53 dB was measured for single-ended baseband inputs and a SNR/sub max/ of 32 dB was measured for differential inputs at 900 MHz, over a 2 MHz bandwidth.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Active-feedback frequency compensation for low-power multi-stage amplifiers 低功率多级放大器的有源反馈频率补偿
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012831
Hoi Lee, P. Mok
{"title":"Active-feedback frequency compensation for low-power multi-stage amplifiers","authors":"Hoi Lee, P. Mok","doi":"10.1109/CICC.2002.1012831","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012831","url":null,"abstract":"This paper describes a novel active-feedback frequency compensation (AFFC) technique for low-power multi-stage amplifiers. With a high-speed active feedback block, the proposed compensation technique significantly improves both the frequency and the transient responses of the amplifier. Implemented by a standard 0.8/spl mu/m CMOS process, a three-stage AFFC amplifier achieves 100dB gain, 4.5MHz gain-bandwidth product, 65/spl deg/ phase margin and 1.5V//spl mu/s slew rate with 0.4mW power consumption when driving a 100pF capacitive load.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115962988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Nearest neighbour interconnect architecture in deep submicron FPGAs 深亚微米fpga中最近邻互连架构
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012766
A. Roopchansingh, Jonathan Rose
{"title":"Nearest neighbour interconnect architecture in deep submicron FPGAs","authors":"A. Roopchansingh, Jonathan Rose","doi":"10.1109/CICC.2002.1012766","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012766","url":null,"abstract":"Several commercial FPGA architectures provide fast connections between adjacent logic blocks that decrease the best-case delay between circuit elements with the goal of increasing overall performance. This paper explores the architecture of these Nearest Neighbour (NN) interconnects to determine topologies, quantities and distances that are best for performance and area. We show that certain architectures can achieve a 7.4% performance improvement at the cost of a 6.3% increase in total FPGA area when fully populated. We also show that a 6.4% improvement can be achieved for a more modest cost of 3.8% increase in area.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"35 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120839183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A multi-bit sigma-delta ADC for multi-mode receivers 用于多模式接收器的多比特σ - δ ADC
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012795
Matthew R. Miller, C. Petrie
{"title":"A multi-bit sigma-delta ADC for multi-mode receivers","authors":"Matthew R. Miller, C. Petrie","doi":"10.1109/CICC.2002.1012795","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012795","url":null,"abstract":"A 2.7-volt /spl Sigma//spl Delta/ modulator with a 6-bit quantizer is fabricated in a 0.18 /spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design 基于环路的多ghz时钟网络互连建模与优化方法
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012758
Xuejue Huang, P. Restle, T. Bucelot, Yu Cao, T. King
{"title":"Loop-based interconnect modeling and optimization approach for multi-GHz clock network design","authors":"Xuejue Huang, P. Restle, T. Bucelot, Yu Cao, T. King","doi":"10.1109/CICC.2002.1012758","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012758","url":null,"abstract":"An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121515870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 80 Mb/s low-power scalable turbo codec core 80mb /s低功耗可扩展turbo编解码器核心
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012851
A. Giulietti, B. Bougard, V. Derudder, S. Dupont, J. Weijers, L. Perre
{"title":"A 80 Mb/s low-power scalable turbo codec core","authors":"A. Giulietti, B. Bougard, V. Derudder, S. Dupont, J. Weijers, L. Perre","doi":"10.1109/CICC.2002.1012851","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012851","url":null,"abstract":"Turbo coding has reached the step in which its astonishing coding gain is already being proven in real applications. Moreover, its applicability to future broadband communications systems is starting to be investigated. In order to be useful in this domain, special turbo codec architectures that cope with low latency, high throughput, low power consumption and high flexibility are needed. This paper presents an implementation of a convolutional turbo codec core based on innovative solutions for those requirements. The combination of a systematic data storage and transfer optimization with high and low level architectural solutions yields a final throughput up to 80.7 Mb/s, a decoding latency of 10 /spl mu/s and a power consumption of less than 50 nJ/bit. The 14.7 mm/sup 2/ full-duplex full-parallel core, implemented in a CMOS 0.18 /spl mu/m technology, is a complete flexible solution for broadband turbo coding.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Spatial averaging and ordering in matched element arrays 匹配元素数组的空间平均和排序
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012874
K. Krishna, W. Bright, D. Dye, K. Muhammad, Yin Hu
{"title":"Spatial averaging and ordering in matched element arrays","authors":"K. Krishna, W. Bright, D. Dye, K. Muhammad, Yin Hu","doi":"10.1109/CICC.2002.1012874","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012874","url":null,"abstract":"Spatial gradients often limit the matching accuracy of element arrays in ADC's and DAC's. We cast. the problem of spatial gradients formally and present a global optimization-based solution that does not require the gradients to be pre-characterized precisely or limit them to being linear and/or quadratic. Si results from a standalone BiCMOS DAC and a CMOS DAC, part of the industry's first DOCSIS 1.1 certified cable modem solution, are presented.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127655576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies 在深亚微米CMOS技术模拟应用的高耐压ESD设计
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012773
Chung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, S. Tu, Mark Chen, Mi-Chang Chang
{"title":"High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies","authors":"Chung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, S. Tu, Mark Chen, Mi-Chang Chang","doi":"10.1109/CICC.2002.1012773","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012773","url":null,"abstract":"A new high voltage tolerant (HVT) ESD design adopts one forward biased P+/N-well diode in series of one stacked NMOS to reduce the total capacitance and maintain the high ESD performance is proposed and implemented by 0.18 /spl mu/m CMOS technologies. The measured HBM and MM ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121352805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A noninvasive channel-select filter for a CMOS Bluetooth receiver 用于CMOS蓝牙接收器的非侵入式通道选择滤波器
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012836
A. Zolfaghari, B. Razavi
{"title":"A noninvasive channel-select filter for a CMOS Bluetooth receiver","authors":"A. Zolfaghari, B. Razavi","doi":"10.1109/CICC.2002.1012836","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012836","url":null,"abstract":"A fourth-order filter incorporates a method of suppressing interferers without filtering the desired signal, relaxing the trade-offs between noise, linearity, and power dissipation. Designed for the baseband of a 2.4 GHz receiver and fabricated in a 0.25 /spl mu/m CMOS technology, the filter exhibits an input-referred noise of 17 nV//spl radic/(Hz) while dissipating 2 mW from a 2.5 V supply and the receiver achieves a noise figure of 6 dB with a power consumption of 17.5 mW.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128958372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology 2.29 gbit /s, 56 mW非流水线Rijndael AES加密IC，采用1.8 V, 0.18 /spl mu/m CMOS技术
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012785
H. Kuo, I. Verbauwhede, P. Schaumont
{"title":"A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology","authors":"H. Kuo, I. Verbauwhede, P. Schaumont","doi":"10.1109/CICC.2002.1012785","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012785","url":null,"abstract":"In October 2000 the National Institute of Standard and Technology (NIST) chose the Rijndael algorithm as the new Advanced Encryption Standard (AES). In this paper we present an ASIC implementation of the Rijndael core. The core includes a non-pipelined encryption datapath with an on-the-fly key schedule data path. At a nominal 1.8 V, the IC runs at 125 MHz resulting in a throughput of 2.29 Gbit/s while consuming 56 mW. At 1.95 V, the chip can operate up to 154 MHz with an equivalent throughput of 2.8 Gbit/s and consumes 82 mW.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128449334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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