用于多模式接收器的多比特σ - δ ADC

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012795

Matthew R. Miller, C. Petrie

{"title":"用于多模式接收器的多比特σ - δ ADC","authors":"Matthew R. Miller, C. Petrie","doi":"10.1109/CICC.2002.1012795","DOIUrl":null,"url":null,"abstract":"A 2.7-volt /spl Sigma//spl Delta/ modulator with a 6-bit quantizer is fabricated in a 0.18 /spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A multi-bit sigma-delta ADC for multi-mode receivers\",\"authors\":\"Matthew R. Miller, C. Petrie\",\"doi\":\"10.1109/CICC.2002.1012795\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2.7-volt /spl Sigma//spl Delta/ modulator with a 6-bit quantizer is fabricated in a 0.18 /spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012795\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012795","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 19

摘要

一个2.7伏/spl Sigma//spl Delta/调制器与一个6位量化器在0.18 /spl μ m CMOS工艺。该调制器利用噪声形动态元件匹配和量化器偏置斩波在宽带宽上实现高线性度。该电路在625 kHz带宽下实现95 dB峰值SFDR和77 dB信噪比，在23 MHz采样频率下消耗30 mW。此外，它在1.92 MHz带宽上实现70 dB信噪比，在46 MHz时功耗为50 mW。

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A multi-bit sigma-delta ADC for multi-mode receivers

A 2.7-volt /spl Sigma//spl Delta/ modulator with a 6-bit quantizer is fabricated in a 0.18 /spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.

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来源期刊

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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