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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)最新文献

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High speed, low power, optoelectronic InP-based HBT integrated circuits 高速，低功耗，光电基于inp的HBT集成电路
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012883
M. Sokolich
{"title":"High speed, low power, optoelectronic InP-based HBT integrated circuits","authors":"M. Sokolich","doi":"10.1109/CICC.2002.1012883","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012883","url":null,"abstract":"The next generation of fiber optic communication systems will require circuits operating at 50 GHz clock rates. InP-based Heterojunction Bipolar Transistors (HBTs) are ideally suited for the relatively low integration levels but high speed and low power required in optoelectronic transceivers. We review material, device and circuit issues related to InP HBT and the significant challenge that exists because communication system requirements are approaching the performance limits of high speed technologies.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115236638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Dual mixer downconversion architecture using complex mixing signals: enabling solutions for software defined radios 使用复杂混频器信号的双混频器下变频架构:实现软件定义无线电的解决方案
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012802
T. Manku, C. Snyder, Michele Ting, Y. Ling, J. Khajehpour, Bill Kung, L. Wong
{"title":"Dual mixer downconversion architecture using complex mixing signals: enabling solutions for software defined radios","authors":"T. Manku, C. Snyder, Michele Ting, Y. Ling, J. Khajehpour, Bill Kung, L. Wong","doi":"10.1109/CICC.2002.1012802","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012802","url":null,"abstract":"A dual mixer architecture using complex mixing functions to perform RF downconversion is described. This architecture eliminates the need for the image-reject and IF filters present in the heterodyne architecture, while achieving better LO leakage, 1/f noise. and second-order intercept performance than the direct conversion architecture. This architecture, implemented in a 1.8 V, 0.18 /spl mu/m CMOS process, achieves a maximum IIP2 of 85 dBm, a baseband 1/f noise corner frequency of less than 100 kHz, a LO-RF leakage equaling -138 dBm, and an operating frequency ranging from 400 MHz to 2.5 GHz.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115374839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A central office combined ADSL-VDSL line driver solution in .35/spl mu/m CMOS 一种在0.35 /spl μ m CMOS中结合ADSL-VDSL线路驱动方案
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012763
T. Piessens, M. Steyaert
{"title":"A central office combined ADSL-VDSL line driver solution in .35/spl mu/m CMOS","authors":"T. Piessens, M. Steyaert","doi":"10.1109/CICC.2002.1012763","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012763","url":null,"abstract":"A central office ADSL-VDSL line driver in a 0.35 /spl mu/m 3.3 V CMOS technology is presented. The chip has a missing tone power ratio (MTPR) over 55 dB driving ADSL signals and can deliver VDSL downstream signals with a bandwidth of 8.6 MHz and an out-of-band PSD of -103 dBm/Hz. The power efficiency is 47% for 100 mW ADSL signals with a crest factor of >5.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121071832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On-chip RF spiral inductors and bandpass filters using active magnetic energy recovery 片上射频螺旋电感和带通滤波器采用主动磁能回收
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012812
Yi-Cheng Wu, M. F. Chang
{"title":"On-chip RF spiral inductors and bandpass filters using active magnetic energy recovery","authors":"Yi-Cheng Wu, M. F. Chang","doi":"10.1109/CICC.2002.1012812","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012812","url":null,"abstract":"We present designs to achieve monolithic integration of high-Q spiral inductors and bandpass filters (BPFs) in standard CMOS technology. The designed transformer-type inductor behaves like an ideal inductor due to the active magnetic feedback from the secondary coil for compensating energy loss in the primary coil. This approach is compatible with mainstream IC technologies and has potential to achieve high-Q reactance with low power, low noise and high linearity. The fabricated inductors exhibit Q/spl sim/3000 between 1.5 to 2.1 GHz. The fabricated BPF shows 3 dB bandwidth of 120 MHz at 1.75 GHz with 3.1 dB in-band gain and 30 dB out-of-band rejection below 1.2 GHZ.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123648984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
The role of monolithic transmission lines in high-speed integrated circuits 单片传输线在高速集成电路中的作用
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012845
B. Razavi
{"title":"The role of monolithic transmission lines in high-speed integrated circuits","authors":"B. Razavi","doi":"10.1109/CICC.2002.1012845","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012845","url":null,"abstract":"This paper describes the role of transmission lines amenable to integration in VLSI technologies and their important circuit implications. First, an overview of microstrips, coplanar lines, and striplines is given and their performance limitations are quantified. Next, modeling and simulation issues are addressed and the role of transmission lines as circuit elements is discussed. Finally, examples of circuits that benefit from monolithic transmission lines are presented.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124343687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Technology trends and challenges for CMOS/system LSIs for the next 10-15 years 未来10-15年CMOS/系统lsi的技术趋势和挑战
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012879
S. Kawamura
{"title":"Technology trends and challenges for CMOS/system LSIs for the next 10-15 years","authors":"S. Kawamura","doi":"10.1109/CICC.2002.1012879","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012879","url":null,"abstract":"There are many challenges which we will be facing in the next 10 to 15 years in developing a state-of-the-art CMOS technology for system LSIs. Among them, lithography, gate-stack, shallow junction and interconnect technologies are major ones. In this paper, these major challenges as well as \"Design Crisis\" and \"Power Crisis\" are discussed in detail from an ITRS (international Technology Roadmap for Semiconductors) perspective, and some potential solutions are described to overcome these challenges and crises.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection 引线海(SoL)的特性和设计，以兼容板级光波导互连
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012885
M. Bakir, H. Reed, A. Mulé, P. Kohl, K. Martin, J. Meindl
{"title":"Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection","authors":"M. Bakir, H. Reed, A. Mulé, P. Kohl, K. Martin, J. Meindl","doi":"10.1109/CICC.2002.1012885","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012885","url":null,"abstract":"Sea of leads (SoL) is a novel ultra-high-density compliant wafer-level packaging technology. The x-y-z compliant input/output (I/O) leads are batch fabricated by simply extending wafer-level batch fabrication of on-chip multilevel interconnect networks. Two-port microwave measurements reveal that the leads exhibit an insertion-loss of less than 0.4dB in the 0.1-45GHz frequency range. In addition, worst-case insertion-loss of signal propagation into and out of the package is 1.15dB at 45GHz. Because the compliant leads are short, their electrical parasitics are minimal. A mixed-signal system-on-a-chip (SoC) requires packages that are compatible with optical interconnect technology. Physical design rules describing SoL design compatibility with board-level optical signal distribution via waveguides are derived.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122241642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A single-chip MPEG-2 codec based on customizable media microprocessor 基于可定制媒体微处理器的单片MPEG-2编解码器
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012789
S. Ishiwata, T. Yamakage, Y. Tsuboi, T. Shimazawa, T. Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, T. Kodama, Nobu Matsumoto, Takayuki Kamei, T. Miyamori, G. Ootomo, M. Matsui
{"title":"A single-chip MPEG-2 codec based on customizable media microprocessor","authors":"S. Ishiwata, T. Yamakage, Y. Tsuboi, T. Shimazawa, T. Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, T. Kodama, Nobu Matsumoto, Takayuki Kamei, T. Miyamori, G. Ootomo, M. Matsui","doi":"10.1109/CICC.2002.1012789","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012789","url":null,"abstract":"A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132059772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A vector DSP for imaging 矢量DSP成像
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012788
John Redford, Bret Bersack, M. Monk, Fred Huettig, D. Fitzgerald
{"title":"A vector DSP for imaging","authors":"John Redford, Bret Bersack, M. Monk, Fred Huettig, D. Fitzgerald","doi":"10.1109/CICC.2002.1012788","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012788","url":null,"abstract":"The CW4011 is an SoC containing a DSP with a novel vector architecture. It exploits the parallelism and narrow data typical of image processing to gain high performance at a low cost and power. It contains eight 32-bit datapaths all working off of a single instruction. It can do 16 16-bit MACs/cycle, and also four 32-bit memory accesses per cycle to 128 KB of on-chip memory. It also contains a serial datapath for handling low-performance code and OS functions. The chip also includes memory, video, and IO interfaces on an industry-standard bus. it is built in 0.18 /spl mu/m CMOS technology, is 7.8 /spl times/ 6.8 mm, runs at 200 MHz (worst-case) and draws less than 500 mW. This gives the best cost-performance of any processor on the market for imaging applications.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132327410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An interpolating sense circuit for molecular memory 分子记忆的插值感测电路
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI: 10.1109/CICC.2002.1012776
Y. Nishida, Wentai Liu
{"title":"An interpolating sense circuit for molecular memory","authors":"Y. Nishida, Wentai Liu","doi":"10.1109/CICC.2002.1012776","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012776","url":null,"abstract":"Presented herein is a novel sensing circuit for multistate molecular memory technologies. The circuit employs an interpolating sensing scheme to achieve low power dissipation and high speed sensing of molecular memory cells. A novel \"reference level offset reduction\" circuit technique is used to reduce the current thresholder's offset to nearly zero. Our interpolating sensing circuit consists of two sense amplifiers and two interpolators. At 2.5 V, the total current for the amplifiers and interpolators is 587 /spl mu/A and 161 /spl mu/A, respectively. The sense circuit exhibits an overall rise time of 41 ns and fall time of 56 ns in TSMC 0.25-/spl mu/m process.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129981582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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