{"title":"未来10-15年CMOS/系统lsi的技术趋势和挑战","authors":"S. Kawamura","doi":"10.1109/CICC.2002.1012879","DOIUrl":null,"url":null,"abstract":"There are many challenges which we will be facing in the next 10 to 15 years in developing a state-of-the-art CMOS technology for system LSIs. Among them, lithography, gate-stack, shallow junction and interconnect technologies are major ones. In this paper, these major challenges as well as \"Design Crisis\" and \"Power Crisis\" are discussed in detail from an ITRS (international Technology Roadmap for Semiconductors) perspective, and some potential solutions are described to overcome these challenges and crises.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Technology trends and challenges for CMOS/system LSIs for the next 10-15 years\",\"authors\":\"S. Kawamura\",\"doi\":\"10.1109/CICC.2002.1012879\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"There are many challenges which we will be facing in the next 10 to 15 years in developing a state-of-the-art CMOS technology for system LSIs. Among them, lithography, gate-stack, shallow junction and interconnect technologies are major ones. In this paper, these major challenges as well as \\\"Design Crisis\\\" and \\\"Power Crisis\\\" are discussed in detail from an ITRS (international Technology Roadmap for Semiconductors) perspective, and some potential solutions are described to overcome these challenges and crises.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012879\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012879","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Technology trends and challenges for CMOS/system LSIs for the next 10-15 years
There are many challenges which we will be facing in the next 10 to 15 years in developing a state-of-the-art CMOS technology for system LSIs. Among them, lithography, gate-stack, shallow junction and interconnect technologies are major ones. In this paper, these major challenges as well as "Design Crisis" and "Power Crisis" are discussed in detail from an ITRS (international Technology Roadmap for Semiconductors) perspective, and some potential solutions are described to overcome these challenges and crises.
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