A central office combined ADSL-VDSL line driver solution in .35/spl mu/m CMOS

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012763

T. Piessens, M. Steyaert

引用次数: 4

Abstract

A central office ADSL-VDSL line driver in a 0.35 /spl mu/m 3.3 V CMOS technology is presented. The chip has a missing tone power ratio (MTPR) over 55 dB driving ADSL signals and can deliver VDSL downstream signals with a bandwidth of 8.6 MHz and an out-of-band PSD of -103 dBm/Hz. The power efficiency is 47% for 100 mW ADSL signals with a crest factor of >5.

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一种在0.35 /spl μ m CMOS中结合ADSL-VDSL线路驱动方案

提出了一种采用0.35 /spl mu/m 3.3 V CMOS技术的中局ADSL-VDSL线路驱动器。该芯片驱动ADSL信号的缺音功率比(MTPR)超过55 dB，可以传输带宽为8.6 MHz的VDSL下行信号，带外PSD为-103 dBm/Hz。对于波峰系数>5的100mw ADSL信号，功率效率为47%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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