2.29 gbit /s, 56 mW非流水线Rijndael AES加密IC，采用1.8 V, 0.18 /spl mu/m CMOS技术

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012785

H. Kuo, I. Verbauwhede, P. Schaumont

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引用次数: 27

摘要

2000年10月，美国国家标准与技术研究所(NIST)选择Rijndael算法作为新的高级加密标准(AES)。在本文中，我们提出了Rijndael核心的ASIC实现。核心包括一个带有动态密钥调度数据路径的非流水线加密数据路径。在标称1.8 V下，IC运行在125 MHz下，吞吐量为2.29 Gbit/s，功耗为56 mW。在1.95 V电压下，芯片工作频率可达154 MHz，等效吞吐量为2.8 Gbit/s，功耗为82 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology

In October 2000 the National Institute of Standard and Technology (NIST) chose the Rijndael algorithm as the new Advanced Encryption Standard (AES). In this paper we present an ASIC implementation of the Rijndael core. The core includes a non-pipelined encryption datapath with an on-the-fly key schedule data path. At a nominal 1.8 V, the IC runs at 125 MHz resulting in a throughput of 2.29 Gbit/s while consuming 56 mW. At 1.95 V, the chip can operate up to 154 MHz with an equivalent throughput of 2.8 Gbit/s and consumes 82 mW.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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