发布求助
文献互助 智能选刊 最新文献

Proceedings Norchip Conference, 2004.最新文献

筛选
英文 中文
Memory hierarchy usage estimation for global loop transformations 对全局循环转换的内存层次结构使用估计
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423883
Qubo Hu, E. Brockmeyer, M. Palkovic, P. G. Kjeldsberg, F. Catthoor
{"title":"Memory hierarchy usage estimation for global loop transformations","authors":"Qubo Hu, E. Brockmeyer, M. Palkovic, P. G. Kjeldsberg, F. Catthoor","doi":"10.1109/NORCHP.2004.1423883","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423883","url":null,"abstract":"Major parts of the power dissipation for data dominated embedded system is due to huge amounts of data transfers to and from large consuming data memories. Global loop transformations play a crucial role in optimizing the memory accesses. By improving regularity and temporal locality of these memory accesses using loop transformations, data can be potentially stored closer to the datapath in smaller less power consuming memories. To steer the selection of which loop transformations to perform, high level memory estimation is used. In state of the art memory estimation techniques the mapping of data to different parts of the memory hierarchy are not considered since these decisions are made in later system design phases. However, estimates of these mapping decisions is crucial, since they greatly influence the consequences of different transformations. In this paper we propose a systematic methodology for hierarchical memory usage estimation which considers also future data mapping decisions for a memory hierarchy. The goal of the estimation is to evaluate global loop transformation decisions for different platforms and keep only the optimal decision (in terms of energy) for each platform. We demonstrate our methodology on a real- life multimedia video coder (QSD PCM) which shows that for 1k layer one memory, a factor of 2 improvement in total energy can be achieved.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125332746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Improving capacitive drive capability of miller compensated amplifier 提高米勒补偿放大器的容性驱动能力
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423872
M. Loikkanen, J. Kostamovaara
{"title":"Improving capacitive drive capability of miller compensated amplifier","authors":"M. Loikkanen, J. Kostamovaara","doi":"10.1109/NORCHP.2004.1423872","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423872","url":null,"abstract":"This paper compares a well-known technique of Separating a capacitive load from the feedback path with a resistor to an alternative separation resistor technique and discusses limitations of both techniques. It is shown with small signal analysis und simulations that the suggested compensation technique has a bandwidth advantage over the traditional one, especially in low power designs. This improvement is achieved at the expense of adding un additional pin to an amplifier package if the separation resistor is located off chip.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122051677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical expression of the efficiency of phantom zero compensation applied on negative-feedback amplifiers 负反馈放大器虚影零补偿效率的解析表达式
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423829
R. Strandberg, J. Piper
{"title":"Analytical expression of the efficiency of phantom zero compensation applied on negative-feedback amplifiers","authors":"R. Strandberg, J. Piper","doi":"10.1109/NORCHP.2004.1423829","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423829","url":null,"abstract":"In this paper methods for behavioral modelling of the effects of small timing errors in DA and time-interleaved AD converters are analyzed and experimented. It is possible to model the spectral effects of the analyzed timing errors without using oversampling or discrete-time derivators.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124771757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multifunction subthreshold gate used for a low power full adder 用于低功率全加法器的多功能亚门限门
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423818
S. Aunet, B. Oelmann, T. Lande, Y. Berg
{"title":"Multifunction subthreshold gate used for a low power full adder","authors":"S. Aunet, B. Oelmann, T. Lande, Y. Berg","doi":"10.1109/NORCHP.2004.1423818","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423818","url":null,"abstract":"This paper presents a full-adder based on realtime reconfigurable CMOS perceptron circuits operating in subthreshold. The Perceptron is based on three output wired inverters that is configured through well biasing. The full-adder is demonstrated by simulations for a 0.12 um CMOS process. Functionality is proven for 200-400 mV power supply voltages. Minimum power consumption is 7.4 nW and power-delay-product 7.8 fJ, for a Vdd of 200 mV, according to simulations.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123320188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A novel 1V-supply, low power, wide tuning range voltage controlled oscillator implemented in 0.18/spl mu/m CMOS technology 一种新颖的1v供电、低功耗、宽调谐范围的压控振荡器，采用0.18/spl mu/m CMOS技术实现
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423821
Z. Toprak, Y. Leblebici
{"title":"A novel 1V-supply, low power, wide tuning range voltage controlled oscillator implemented in 0.18/spl mu/m CMOS technology","authors":"Z. Toprak, Y. Leblebici","doi":"10.1109/NORCHP.2004.1423821","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423821","url":null,"abstract":"This paper describes the design of a very low power low phase noise, wide turning range oscillator for battery operated equipment. The proposed design allows an implementation of voltage controlled ring oscillator (VCO) operating at I Volt supply voltage. Implemented in 0.18μm CMOS technology, operating at 50MHz to 250MHz, the proposed VCO has a tuning range of almost 50%. At 125MHz the phase noise of the VCO is - 98dBc/Hz@1MHz offsert the carrier consuming very low power, 0.41mW. The silicon area of the designed VCO is 35μm by 95μm.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122987615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon self-switching-device based logic gates operating at room temperature 室温下工作的基于硅自开关器件的逻辑门
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423817
M. Åberg, J. Saijets, E. Pursula, M. Prunnila, J. Ahopelto
{"title":"Silicon self-switching-device based logic gates operating at room temperature","authors":"M. Åberg, J. Saijets, E. Pursula, M. Prunnila, J. Ahopelto","doi":"10.1109/NORCHP.2004.1423817","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423817","url":null,"abstract":"This paper presents first functional operational results of logic gates based on Silicon nano scale self switching devices (SSDs) and side gated transistors (SGTs). The devices are manufactured with Silicon-on- Insulator (SOU technology and are operative in room temperature. The circuits show correct logic operation. The performance parameters are still short of practical values, but ways of bringing them to acceptable level for real applications are discussed.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114486575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A modified shield-based test fixture for silicon-on-insulator (SOI) to mitigate the uncertainties of the parallel parasitics 一种改进的基于屏蔽的绝缘体上硅(SOI)测试夹具，以减轻并联寄生的不确定性
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423837
T. Kaija, E. Ristolainen
{"title":"A modified shield-based test fixture for silicon-on-insulator (SOI) to mitigate the uncertainties of the parallel parasitics","authors":"T. Kaija, E. Ristolainen","doi":"10.1109/NORCHP.2004.1423837","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423837","url":null,"abstract":"A modified ground-shielded test fixture is proposed to mitigate the discrepancies of the conventional ground-shielded test future caused by the variation of the vertical oxide thickness. In-situ calibration and immitance correction require that the probe tip to device under test (DUT) area -transition is identical in every test fixture. By employing the proposed test fixture, reduced parasitic uncertainty between test fixtures can he achieved while the capacitive signal loading is significantly decreased while the good isolation properties are remained.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122099925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Histogram based background correction of ADC 基于直方图的ADC背景校正
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423831
T. Rahkonen, M. Kangas
{"title":"Histogram based background correction of ADC","authors":"T. Rahkonen, M. Kangas","doi":"10.1109/NORCHP.2004.1423831","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423831","url":null,"abstract":"Histogran based, hardware-efficient background calibration method of ADC is introduced in this paper. Theory of the calibration is described first, following by description of the simulation setup using binary weighted eight bit ADC. Simulation results are introduced at the end of the paper.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"129 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124006135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 14b 200MHz IF-sampling A/D converter with 79.9dB SFDR 14b 200MHz中频采样A/D转换器，79.9dB SFDR
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423850
V. Hakkarainen, M. Aho, L. Sumanen, M. Waltati, K. Halonen
{"title":"A 14b 200MHz IF-sampling A/D converter with 79.9dB SFDR","authors":"V. Hakkarainen, M. Aho, L. Sumanen, M. Waltati, K. Halonen","doi":"10.1109/NORCHP.2004.1423850","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423850","url":null,"abstract":"This paper presents a 14-bit, 100-MS/s time-interleaved pipeline ADC, which samples input signal from 210-MHz IF-band. Digital self-calibration is employed to compensate gain mismatch and offset between time-interleaved channels as well as mismatches arised from a single ADC channel. A timing skew-insensitive parallel S/H circuit is utilized in order to avoid timing skew between parallel ADC channels. The ADC, fabricated in a 0.35- pm BiCMOS (SiGe) takes an area of 10.2 mm2 reaches an ENOB of 11.4 bits with a 79.9-dB SFDR at 192.5- MHz input and draws 1.4 W from a 3.0-V supply.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125324030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Programmable analog integrated circuit 可编程模拟集成电路
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423832
C. Wulff, R. Erstad, T. Ytterdal
{"title":"Programmable analog integrated circuit","authors":"C. Wulff, R. Erstad, T. Ytterdal","doi":"10.1109/NORCHP.2004.1423832","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423832","url":null,"abstract":"The protorype of a Programmable Analog Integrated Circuit (PAnIC) for use in remote laboratories is presented. The validity of using programmable analog integrated circuits to allow students to run remote experiments on different circuits is verified.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126362270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信